From 1615d4f1d461b5796d92b8333678d5680b1adede Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 26 May 2022 15:55:03 +0100 Subject: [PATCH] Revert "svp64.py: simplify CR sv_extra and field processing" This reverts commit d56564910763a69f113615bedf94022da9457de5. --- src/openpower/sv/trans/svp64.py | 52 +++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 59d4c8ee..f8c3c7ac 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -517,7 +517,7 @@ class SVP64Asm: # https://libre-soc.org/openpower/sv/ldst/ # encode SV-GPR and SV-FPR field into extra, v3.0field - if rtype in ('GPR', 'FPR'): + if rtype in ['GPR', 'FPR']: sv_extra, field = get_extra_gpr(etype, regmode, field) # now sanity-check. EXTRA3 is ok, EXTRA2 has limits # (and shrink to a single bit if ok) @@ -541,11 +541,47 @@ class SVP64Asm: # EXTRA3 vector bit needs marking sv_extra |= 0b100 - elif rtype in ('CR_3bit', 'CR_5bit'): - if rtype == "CR_5bit": - cr_subfield = field & 0b11 - field = field >> 2 # strip bottom 2 bits + # encode SV-CR 3-bit field into extra, v3.0field + elif rtype == 'CR_3bit': + sv_extra, field = get_extra_cr_3bit(etype, regmode, field) + # now sanity-check (and shrink afterwards) + if etype == 'EXTRA2': + if regmode == 'scalar': + # range is CR0-CR15 in increments of 1 + assert (sv_extra >> 1) == 0, \ + "scalar CR %s cannot fit into EXTRA2 %s" % \ + (rname, str(extras[extra_idx])) + # all good: encode as scalar + sv_extra = sv_extra & 0b01 + else: + # range is CR0-CR127 in increments of 16 + assert sv_extra & 0b111 == 0, \ + "vector CR %s cannot fit into EXTRA2 %s" % \ + (rname, str(extras[extra_idx])) + # all good: encode as vector (bit 2 set) + sv_extra = 0b10 | (sv_extra >> 3) + else: + if regmode == 'scalar': + # range is CR0-CR31 in increments of 1 + assert (sv_extra >> 2) == 0, \ + "scalar CR %s cannot fit into EXTRA2 %s" % \ + (rname, str(extras[extra_idx])) + # all good: encode as scalar + sv_extra = sv_extra & 0b11 + else: + # range is CR0-CR127 in increments of 8 + assert sv_extra & 0b11 == 0, \ + "vector CR %s cannot fit into EXTRA2 %s" % \ + (rname, str(extras[extra_idx])) + # all good: encode as vector (bit 3 set) + sv_extra = 0b100 | (sv_extra >> 2) + # encode SV-CR 5-bit field into extra, v3.0field + # *sigh* this is the same as 3-bit except the 2 LSBs are + # passed through + elif rtype == 'CR_5bit': + cr_subfield = field & 0b11 + field = field >> 2 # strip bottom 2 bits sv_extra, field = get_extra_cr_3bit(etype, regmode, field) # now sanity-check (and shrink afterwards) if etype == 'EXTRA2': @@ -578,10 +614,8 @@ class SVP64Asm: (rname, str(extras[extra_idx])) # all good: encode as vector (bit 3 set) sv_extra = 0b100 | (sv_extra >> 2) - - if rtype == "CR_5bit": - # reconstruct the actual 5-bit CR field - field = (field << 2) | cr_subfield + # reconstruct the actual 5-bit CR field + field = (field << 2) | cr_subfield else: print("no type match", rtype) -- 2.30.2