From 161a6bd05555bb45f4735ad61b399b1510e9462f Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 29 Jan 2021 19:10:09 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 64b3717fa..190dbafe9 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -49,6 +49,9 @@ Form: SVL-Form (see [[isatables/fields.text]]) Note that imm (SVi) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero. Setting bit 22 or 23 causes an illegal exception. +`ms` - bit 25 - allows for setting of MVL. `vs` - bit 24 - allows for +setting of VL. + Note that in immediate setting mode VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1. 0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SV SPRs|sv/sprs]] Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise -- 2.30.2