From 1641cfb37578643464049460f885faa2feb10700 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 18:39:35 +0100 Subject: [PATCH] move regspec function to separate module --- src/soc/decoder/power_regspec_map.py | 98 ++++++++++++++++++++++++++++ src/soc/fu/regspec.py | 91 -------------------------- 2 files changed, 98 insertions(+), 91 deletions(-) create mode 100644 src/soc/decoder/power_regspec_map.py diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py new file mode 100644 index 00000000..dec4b3cd --- /dev/null +++ b/src/soc/decoder/power_regspec_map.py @@ -0,0 +1,98 @@ +"""regspec_decode + +function for the relationship between regspecs and Decode2Execute1Type + +see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs +""" +from nmigen import Const +from soc.regfile.regfiles import XERRegs, FastRegs + + +def regspec_decode(e, regfile, name): + """regspec_decode + + this function encodes the understanding (relationship) between + Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2). + + based on the regspec, which contains the register file name and register + name, return a tuple of: + + * how the decoder should determine whether the Function Unit needs + a Regport or not + * which Regfile port should be read to get that data + * when it comes to writing: likewise, which Regfile port should be written + + Note that some of the port numbering encoding is *unary*. in the case + of "Full Condition Register", it's a full 8-bit mask of read/write-enables. + This actually matches directly with the XFX field in MTCR, and at + some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO). + + For the INT and CR numbering, these are expressed in binary in the + instruction (note however that XFX in MTCR is unary-masked!) + + XER is implicitly-encoded based on whether the operation has carry or + overflow. + + FAST regfile is, again, implicitly encoded, back in PowerDecode2, based + on the type of operation (see DecodeB for an example). + + The SPR regfile on the other hand is *binary*-encoded, and, furthermore, + has to be "remapped". + """ + + if regfile == 'INT': + # Int register numbering is *unary* encoded + if name == 'ra': # RA + return e.read_reg1.ok, 1<