From 16512f6efd768c4aaada5cfdbdb78d96b330b002 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 7 Jul 2019 00:59:34 +0000 Subject: [PATCH] hdl.dsl: gracefully handle FSM with no states. --- nmigen/hdl/dsl.py | 2 ++ nmigen/test/test_hdl_dsl.py | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 5b82089..415ad95 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -337,6 +337,8 @@ class Module(_ModuleBuilderRoot, Elaboratable): if name == "FSM": fsm_signal, fsm_reset, fsm_encoding, fsm_decoding, fsm_states = \ data["signal"], data["reset"], data["encoding"], data["decoding"], data["states"] + if not fsm_states: + return fsm_signal.nbits = bits_for(len(fsm_encoding) - 1) if fsm_reset is None: fsm_signal.reset = fsm_encoding[next(iter(fsm_states))] diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 04f7e8c..714eb47 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -449,6 +449,14 @@ class DSLTestCase(FHDLTestCase): ) """) + def test_FSM_empty(self): + m = Module() + with m.FSM(): + pass + self.assertRepr(m._statements, """ + () + """) + def test_FSM_wrong_redefined(self): m = Module() with m.FSM(): -- 2.30.2