From 1656179a803f93fc7cf2254fbc7d3ff03f8c6ee9 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 22 Apr 2019 00:46:45 -0700 Subject: [PATCH] rename LFSR -> LFSR2 --- TLB/src/{LFSR.py => LFSR2.py} | 0 TLB/test/{test_LFSR.py => test_LFSR2.py} | 6 +++--- 2 files changed, 3 insertions(+), 3 deletions(-) rename TLB/src/{LFSR.py => LFSR2.py} (100%) rename TLB/test/{test_LFSR.py => test_LFSR2.py} (92%) diff --git a/TLB/src/LFSR.py b/TLB/src/LFSR2.py similarity index 100% rename from TLB/src/LFSR.py rename to TLB/src/LFSR2.py diff --git a/TLB/test/test_LFSR.py b/TLB/test/test_LFSR2.py similarity index 92% rename from TLB/test/test_LFSR.py rename to TLB/test/test_LFSR2.py index 84af24da..f7eabc19 100644 --- a/TLB/test/test_LFSR.py +++ b/TLB/test/test_LFSR2.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: LGPL-2.1-or-later # See Notices.txt for copyright information -from ..src.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3 +from ..src.LFSR2 import LFSR, LFSRPolynomial, LFSR_POLY_3 from nmigen.back.pysim import Simulator, Delay, Tick import unittest @@ -28,8 +28,8 @@ class TestLFSR(unittest.TestCase): module = LFSR(LFSR_POLY_3) traces = [module.state, module.enable] with Simulator(module, - vcd_file=open("Waveforms/test_LFSR.vcd", "w"), - gtkw_file=open("Waveforms/test_LFSR.gtkw", "w"), + vcd_file=open("Waveforms/test_LFSR2.vcd", "w"), + gtkw_file=open("Waveforms/test_LFSR2.gtkw", "w"), traces=traces) as sim: sim.add_clock(1e-6, 0.25e-6) delay = Delay(1e-7) -- 2.30.2