From 16692903cbf57da5c7180b0a9f3788f152aa86bc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 20 May 2018 14:08:35 +0100 Subject: [PATCH] update slides --- simple_v_extension/simple_v_chennai_2018.tex | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index b0e6cd992..e85078d13 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -260,14 +260,17 @@ for (int i = 0; i < VL; ++i) } -\frame{\frametitle{slide} +\frame{\frametitle{Summary} \begin{itemize} - \item \vspace{10pt} - \end{itemize} - Considerations:\vspace{10pt} - \begin{itemize} - \item \vspace{10pt} + \item Designed for simplicity (graded levels of complexity)\vspace{10pt} + \item Fits RISC-V ethos: do more with less\vspace{10pt} + \item Reduces SIMD ISA proliferation by 3-4 orders of magnitude + (without SIMD downsides or sacrificing speed trade-off)\vspace{10pt} + \item Covers 98\% of RVV, allows RVV to fit "on top"\vspace{10pt} + \item Huge range of implementor freedom and flexibility\vspace{10pt} + \item Not designed for supercomputing (that's RVV), designed for + in between: DSPs, RV32E, Embedded 3D GPUs etc.\vspace{10pt} \end{itemize} } -- 2.30.2