From 1678da53906fce0a992493fa48b85310c37ebd3d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 May 2019 10:00:50 +0100 Subject: [PATCH] add mul and shift to simulation --- src/experiment/score6600.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 5ba2861b..620841ef 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -45,8 +45,8 @@ class CompUnits(Elaboratable): # Int ALUs add = ALU(self.rwid) sub = ALU(self.rwid) - m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add) - m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub) + m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add) + m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub) int_alus = [comp1, comp2] m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add @@ -313,6 +313,8 @@ class Scoreboard(Elaboratable): IADD = 0 ISUB = 1 +IMUL = 2 +ISHF = 3 class RegSim: def __init__(self, rwidth, nregs): @@ -323,9 +325,14 @@ class RegSim: src1 = self.regs[src1] src2 = self.regs[src2] if op == IADD: - val = (src1 + src2) & ((1<<(self.rwidth))-1) + val = (src1 + src2) elif op == ISUB: - val = (src1 - src2) & ((1<<(self.rwidth))-1) + val = (src1 - src2) + elif op == IMUL: + val = (src1 * src2) + elif op == ISHF: + val = (src1 << (src2 & self.rwidth)) + val &= ((1<<(self.rwidth))-1) self.regs[dest] = val def setval(self, dest, val): -- 2.30.2