From 167a876c4fb9fc8c0d51c6f2696dc732ac7b5984 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 9 Sep 2016 18:35:09 -0700
Subject: [PATCH] allow MAFDC bits in MISA to be modified

---
 riscv/processor.cc | 18 ++++++++++++++++++
 riscv/processor.h  |  1 +
 2 files changed, 19 insertions(+)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6d0b983..1a41f60 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -109,6 +109,8 @@ void processor_t::parse_isa_string(const char* str)
   // advertise support for supervisor and user modes
   isa |= 1L << ('s' - 'a');
   isa |= 1L << ('u' - 'a');
+
+  max_isa = isa;
 }
 
 void state_t::reset()
@@ -392,6 +394,22 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
     case CSR_MBADADDR: state.mbadaddr = val; break;
+    case CSR_MISA: {
+      if (!(val & (1L << ('F' - 'A'))))
+        val &= ~(1L << ('D' - 'A'));
+
+      // allow MAFDC bits in MISA to be modified
+      reg_t mask = 0;
+      mask |= 1L << ('M' - 'A');
+      mask |= 1L << ('A' - 'A');
+      mask |= 1L << ('F' - 'A');
+      mask |= 1L << ('D' - 'A');
+      mask |= 1L << ('C' - 'A');
+      mask &= max_isa;
+
+      isa = (val & mask) | (isa & ~mask);
+      break;
+    }
     case CSR_TSELECT:
       if (val < state.num_triggers) {
         state.tselect = val;
diff --git a/riscv/processor.h b/riscv/processor.h
index 4d8dd64..8a9ff47 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -286,6 +286,7 @@ private:
   unsigned max_xlen;
   unsigned xlen;
   reg_t isa;
+  reg_t max_isa;
   std::string isa_string;
   bool histogram_enabled;
   bool halt_on_reset;
-- 
2.30.2