From 167dc92b876bca1d61298fd00e97a4957ff2a07e Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Fri, 24 Jun 2022 21:49:23 +0300 Subject: [PATCH] svp64.py: support svindex instruction --- src/openpower/sv/trans/svp64.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index b0a1686f..6e841e5e 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -304,6 +304,29 @@ class SVP64Asm: yield ".long 0x%x" % insn return + # this is a *32-bit-only* instruction. is a convenience instruction + # that reduces instruction count for Indexed REMAP Mode. + # it is *not* a 64-bit-prefixed Vector instruction (no sv.svindex), + # it is a Vector *control* instruction. + # note: EXT022 is the "sandbox" major opcode so it's fine to add + # note that the dimension field one subtracted + if opcode == "svindex": + # 1.6.28 SVI-FORM + # |0 |6 |11 |16 |21 |23|24|25|26 31| + # | PO | RS |mask | SVd |ew |yx|mm|sk| XO | + fields = list(map(int, fields)) + insn = 22 << (31-5) # opcode 22, bits 0-5 + insn |= fields[0] << (31-10) # RS , bits 6-10 + insn |= fields[1] << (31-15) # mask , bits 11-15 + insn |= (fields[2]-1) << (31-20) # SVd , bits 16-20 + insn |= fields[3] << (31-22) # ew , bits 21-22 + insn |= fields[4] << (31-23) # yx , bit 23 + insn |= fields[5] << (31-24) # mm , bit 24 + insn |= fields[6] << (31-25) # sk , bit 25 + log("svindex", bin(insn)) + yield ".long 0x%x" % insn + return + # this is a *32-bit-only* instruction. it updates the SVSHAPE SPR # it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap), # it is a Vector *control* instruction. @@ -1371,6 +1394,7 @@ if __name__ == '__main__': 'absdacu 3,12,5', 'absdacs 3,12,5', 'cprop 3,12,5', + 'svindex 0,0,1,0,0,0,0', ] isa = SVP64Asm(lst, macros=macros) log("list", list(isa)) -- 2.30.2