From 16a0aebcadf4a400ea4e430f6d74f7b791891110 Mon Sep 17 00:00:00 2001
From: Pawel Sagan <psagan@internships.antmicro.com>
Date: Thu, 25 Jun 2020 14:32:50 +0200
Subject: [PATCH] i2s: Fix the incorrect TX fifo almost empty offset

---
 litex/soc/cores/i2s.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index 14ba8415..a5dde4ca 100644
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -495,7 +495,7 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                 p_DEVICE              = "7SERIES",
                 p_FIFO_SIZE           = "18Kb",
                 p_DATA_WIDTH          = fifo_data_width,
-                p_ALMOST_EMPTY_OFFSET = fifo_depth,
+                p_ALMOST_EMPTY_OFFSET = (512 - fifo_depth),
                 p_ALMOST_FULL_OFFSET  = 8,
                 p_DO_REG              = 0,
                 i_CLK         = ClockSignal(),
-- 
2.30.2