From 16a7b1928ea75f564f168e5b8dad1849f98af66a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 9 Aug 2023 22:37:58 +0100 Subject: [PATCH] --- 3d_gpu/architecture/inorder_model.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn index fd1ece72d..a848c4e4e 100644 --- a/3d_gpu/architecture/inorder_model.mdwn +++ b/3d_gpu/architecture/inorder_model.mdwn @@ -8,7 +8,7 @@ approximately 10-15 lines of python code to get it actually running a first unit The Libre-SOC TestIssuer core utilises a Finite-State Machine (FSM) to control the fetch/dec/issue/exec -pipelines, with only one pipeline being active at any given time. This is good +Computational Units, with only one such CompUnit (a FSM or a pipeline) being active at any given time. This is good for debugging the HDL, but severly restricts performance as a single instruction will take tens of clock cycles to complete. In-development (Andrey to research and link to the relevant bugreport) is an in-order -- 2.30.2