From 16c3e502aadf81ad8d5b7a8f298db4b7ea905567 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Dec 2021 01:57:20 +0000 Subject: [PATCH] forgot to connect up I-Cache to MMU --- src/soc/fu/mmu/fsm.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index e1f2b2ee..a9b5df22 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -73,13 +73,14 @@ class FSMMMUStage(ControlBase): assert hasattr(self, "dcache"), "remember to call set_ldst_interface" m = super().elaborate(platform) comb, sync = m.d.comb, m.d.sync - dcache = self.dcache + dcache, icache = self.dcache, self.icache + ldst = self.ldst # managed externally: do not add here - # link mmu and dcache together + # link mmu, dcache and icache together m.submodules.mmu = mmu = self.mmu - ldst = self.ldst # managed externally: do not add here m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType + m.d.comb += icache.m_in.eq(mmu.i_out) # MMUToICacheType l_in, l_out = mmu.l_in, mmu.l_out d_in, d_out = dcache.d_in, dcache.d_out -- 2.30.2