From 16ef2669382877afc198ff382633ad75c34be5dc Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 21 Oct 2021 20:49:06 -0700 Subject: [PATCH] add description of SimdSlice and why it needs padding --- 3d_gpu/architecture/dynamic_simd.mdwn | 1 + 3d_gpu/architecture/dynamic_simd/slice.mdwn | 124 ++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 3d_gpu/architecture/dynamic_simd/slice.mdwn diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index 52f75e3f1..df87177ba 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -237,6 +237,7 @@ constructs in the form described above. * [[dynamic_simd/mul]] * [[dynamic_simd/shift]] * [[dynamic_simd/logicops]] Horizontal reduction: some all xor bool +* [[dynamic_simd/slice]] nmigen ast.Slice # Integration with nmigen: "Type 2" (dsl.Module) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn new file mode 100644 index 000000000..48cebda9e --- /dev/null +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -0,0 +1,124 @@ +# Dynamic Partitioned Slice (`SimdSlice`) + +In order to match the semantics of nmigen's `Slice` class, `SimdSlice` has to have each element of the result have +exactly the same `Shape` as the result of slicing the input `SimdSignal`'s corresponding element. + +## Example code: + +```python +a = SimdSignal(...) +a_s = a.sig # shorthand to make table smaller +b = a[3:6] +b_s = a.sig # shorthand to make table smaller +``` + +## `a`'s Elements: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bit #63⁠…⁠5655⁠…⁠4847⁠…⁠4039⁠…⁠3231⁠…⁠2423⁠…⁠1615⁠…⁠87⁠…⁠0
ElWid: 8-bita_s[56:64]a_s[48:56]a_s[40:48]a_s[32:40]a_s[24:32]a_s[16:24]a_s[8:16]a_s[0:8]
ElWid: 16-bita_s[48:64]a_s[32:48]a_s[16:32]a_s[0:16]
ElWid: 32-bita_s[32:64]a_s[0:32]
ElWid: 64-bita_s[0:64]
+ +So, slicing bits `3:6` of a 32-bit element of `a` must, because we have to match nmigen, produce a 3-bit element, which might seem like no problem, however, slicing bits `3:6` of a 16-bit element of a 64-bit `SimdSignal` must *also* produce a 3-bit element, so, in order to get a `SimdSignal` where *all* elements are 3-bit elements, as required by `SimdSlice`'s output, we have to introduce padding: + +## `b`'s Elements: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bit #23⁠…⁠2120⁠…⁠1817⁠…⁠1514⁠…⁠1211⁠…⁠98⁠…⁠65⁠…⁠32⁠…⁠0
ElWid: 8-bitb_s[21:24]b_s[18:21]b_s[15:18]b_s[12:15]b_s[9:12]b_s[6:9]b_s[3:6]b_s[0:3]
ElWid: 16-bitPaddingb_s[18:21]Paddingb_s[12:15]Paddingb_s[6:9]Paddingb_s[0:3]
ElWid: 32-bitPaddingb_s[12:15]Paddingb_s[0:3]
ElWid: 64-bitPaddingb_s[0:3]
+ + -- 2.30.2