From 16f9ce54a0d172f5386bc221331ccac2ecc8ed21 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 Aug 2020 14:06:06 +0000 Subject: [PATCH] rename clk/rst to coresync_clk/rst, resize height of DIV to 2000 --- experiments9/doDesign.py | 52 ++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 9871d13..53602e7 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -59,7 +59,7 @@ def scriptMain ( **kw ): AE = IoPin.A_END alup=[ - (IW | AB, 'clk' , 0 ), + (IW | AB, 'coresync_clk' , 0 ), (IW | AB, 'cu_issue_i' , 0 ), (IW | AB, 'oper_i_alu_alu0_imm_data_imm_ok' , 0 ), (IW | AB, 'oper_i_alu_alu0_invert_a' , 0 ), @@ -73,7 +73,7 @@ def scriptMain ( **kw ): (IW | AB, 'oper_i_alu_alu0_rc_rc_ok' , 0 ), (IW | AB, 'oper_i_alu_alu0_write_cr0' , 0 ), (IW | AB, 'oper_i_alu_alu0_zero_a' , 0 ), - (IW | AB, 'rst' , 0 ), + (IW | AB, 'coresync_rst' , 0 ), (IW | AB, 'src3_i' , 0 ), (IW | AB, 'oper_i_alu_alu0_input_carry({})' , 0, l( 10.0), 2), (IW | AB, 'src4_i({})' , 0, l( 10.0), 2), @@ -115,7 +115,7 @@ def scriptMain ( **kw ): #rvalue = blockAlu0.build() divp=[ - (IN , 'clk' , l(4500.0) ), + (IN , 'coresync_clk' , l(4500.0) ), (IW | AB, 'cu_issue_i' , 0, l(20) ), (IW | AB, 'oper_i_alu_div0_imm_data_imm_ok' , 0, l(20) ), (IW | AB, 'oper_i_alu_div0_invert_a' , 0, l(20) ), @@ -129,12 +129,12 @@ def scriptMain ( **kw ): (IW | AB, 'oper_i_alu_div0_rc_rc_ok' , 0, l(20) ), (IW | AB, 'oper_i_alu_div0_write_cr0' , 0, l(20) ), (IW | AB, 'oper_i_alu_div0_zero_a' , 0, l(20) ), - (IW | AB, 'rst' , 0, l(20) ), + (IW | AB, 'coresync_rst' , 0, l(20) ), (IW | AB, 'src3_i' , 0, l(20) ), (IW | AB, 'cu_rd_go_i({})' , 0, l(10.0), 3), (IW | AB, 'cu_rdmaskn_i({})' , 0, l(10.0), 3), (IW | AB, 'cu_wr_go_i({})' , 0, l(10.0), 4), - (IW | AB, 'oper_i_alu_div0_data_len' , 0, l(10.0), 7), + (IW | AB, 'oper_i_alu_div0_data_len({})' , 0, l(10.0), 7), (IW | AB, 'oper_i_alu_div0_insn_type({})' , 0, l(10.0), 7), (IW | AB, 'oper_i_alu_div0_fn_unit({})' , 0, l(10.0), 11), (IW | AB, 'oper_i_alu_div0_insn({})' , 0, l(10.0), 32), @@ -158,12 +158,12 @@ def scriptMain ( **kw ): blockDiv0.state.cfg.etesian.uniformDensity = True blockDiv0.state.cfg.etesian.spaceMargin = 0.10 blockDiv0.state.cfg.katana.searchHalo = 1 - blockDiv0.state.fixedHeight = l(5000) + blockDiv0.state.fixedHeight = l(2000) blockDiv0.state.useSpares = False #rvalue = blockDiv0.build() mulp=[ - (IN , 'clk' , l(4500.0) ), + (IN , 'coresync_clk' , l(4500.0) ), (IW | AB, 'cu_issue_i' , 0, l(20) ), (IW | AB, 'oper_i_alu_mul0_imm_data_imm_ok' , 0, l(20) ), (IW | AB, 'oper_i_alu_mul0_invert_a' , 0, l(20) ), @@ -176,7 +176,7 @@ def scriptMain ( **kw ): (IW | AB, 'oper_i_alu_mul0_rc_rc_ok' , 0, l(20) ), (IW | AB, 'oper_i_alu_mul0_write_cr0' , 0, l(20) ), (IW | AB, 'oper_i_alu_mul0_zero_a' , 0, l(20) ), - (IW | AB, 'rst' , 0, l(20) ), + (IW | AB, 'coresync_rst' , 0, l(20) ), (IW | AB, 'src3_i' , 0, l(20) ), (IW | AB, 'cu_rd_go_i({})' , 0, l(10.0), 3), (IW | AB, 'cu_rdmaskn_i({})' , 0, l(10.0), 3), @@ -209,12 +209,12 @@ def scriptMain ( **kw ): #rvalue = blockMul0.build() branchp=[ - (IN, 'clk' , l( 805.0) ), + (IN, 'coresync_clk' , l( 805.0) ), (IW , 'cu_issue_i' , l( 30.0) ), (IW , 'oper_i_alu_branch0_imm_data_imm_ok' , l( 40.0) ), (IW , 'oper_i_alu_branch0_is_32bit' , l( 70.0) ), (IW , 'oper_i_alu_branch0_lk' , l( 150.0) ), - (IW , 'rst' , l( 160.0) ), + (IW , 'coresync_rst' , l( 160.0) ), (IW , 'src3_i({})' , l( 180.0), l( 10.0), 4), (IW , 'cu_rd_go_i({})' , l( 270.0), l( 10.0), 3), (IW , 'cu_rdmaskn_i({})' , l( 310.0), l( 10.0), 3), @@ -247,11 +247,11 @@ def scriptMain ( **kw ): blockCr0 = Block.create \ ( cr0 , ioPins=[ - (IN, 'clk' , l( 805.0) ) + (IN, 'coresync_clk' , l( 805.0) ) , (IW , 'cu_issue_i' , l( 30.0) ) , (IW , 'oper_i_alu_cr0_read_cr_whole' , l( 40.0) ) , (IW , 'oper_i_alu_cr0_write_cr_whole' , l( 70.0) ) - , (IW , 'rst' , l( 160.0) ) + , (IW , 'coresync_rst' , l( 160.0) ) , (IW , 'src4_i({})' , l( 180.0), l( 10.0), 4) , (IW , 'src5_i({})' , l( 220.0), l( 10.0), 4) , (IW , 'src6_i({})' , l( 260.0), l( 10.0), 4) @@ -284,7 +284,7 @@ def scriptMain ( **kw ): blockLdst0 = Block.create \ ( ldst0 , ioPins=[ - (IN , 'clk' , l(805.0) ) + (IN , 'coresync_clk' , l(805.0) ) , (IW | AB, 'cu_ad_go_i' , 0, l(20), 1) , (IW | AB, 'cu_issue_i' , 0, l(20), 1) , (IW | AB, 'ldst_port0_addr_exc_o' , 0, l(20), 1) @@ -300,7 +300,7 @@ def scriptMain ( **kw ): , (IW | AB, 'oper_i_ldst_ldst0_rc_rc_ok' , 0, l(20), 1) , (IW | AB, 'oper_i_ldst_ldst0_sign_extend' , 0, l(20), 1) , (IW | AB, 'oper_i_ldst_ldst0_zero_a' , 0, l(20), 1) - , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'cu_st_go_i' , 0, l(20), 1) , (IW | AB, 'oper_i_ldst_ldst0_ldst_mode({})' , 0, l(20), 2) , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 3) @@ -343,7 +343,7 @@ def scriptMain ( **kw ): blockLogical0 = Block.create \ ( logical0 , ioPins=[ - (IN , 'clk' , l(805.0) ) + (IN , 'coresync_clk' , l(805.0) ) , (IW | AB, 'cu_issue_i' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_logical0_invert_a' , 0, l(20), 1) @@ -357,7 +357,7 @@ def scriptMain ( **kw ): , (IW | AB, 'oper_i_alu_logical0_rc_rc_ok' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_logical0_write_cr0' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_logical0_zero_a' , 0, l(20), 1) - , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_logical0_input_carry({})' , 0, l(20), 2) , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 2) , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 2) @@ -391,7 +391,7 @@ def scriptMain ( **kw ): blockShiftrot0 = Block.create \ ( shiftrot0 , ioPins=[ - (IN , 'clk' , l(805.0) ) + (IN , 'coresync_clk' , l(805.0) ) , (IW | AB, 'cu_issue_i' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_shift_rot0_input_cr' , 0, l(20), 1) @@ -403,7 +403,7 @@ def scriptMain ( **kw ): , (IW | AB, 'oper_i_alu_shift_rot0_output_cr' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc_ok' , 0, l(20), 1) - , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20), 2) , (IW | AB, 'src4_i({})' , 0, l(10), 2) , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4) @@ -438,10 +438,10 @@ def scriptMain ( **kw ): blockSpr0 = Block.create \ ( spr0 , ioPins=[ - (IN , 'clk' , l(805.0) ) + (IN , 'coresync_clk' , l(805.0) ) , (IW | AB, 'cu_issue_i' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1) - , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'src4_i' , 0, l(10), 1) , (IW | AB, 'src5_i({})' , 0, l(10), 2) , (IW | AB, 'src6_i({})' , 0, l(10), 2) @@ -482,10 +482,10 @@ def scriptMain ( **kw ): blockTrap0 = Block.create \ ( trap0 , ioPins=[ - (IN , 'clk' , l(805.0) ) + (IN , 'coresync_clk' , l(805.0) ) , (IW | AB, 'cu_issue_i' , 0, l(20), 1) , (IW | AB, 'oper_i_alu_trap0_is_32bit' , 0, l(20), 1) - , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4) , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4) , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 5) @@ -525,8 +525,8 @@ def scriptMain ( **kw ): fast = af.getCell( 'fast', CRL.Catalog.State.Views ) blockFast = Block.create \ ( fast - , ioPins=[ (IN , 'clk' , l(805.0) ) - , (IW | AB, 'rst' , 0, l(20), 1) + , ioPins=[ (IN , 'coresync_clk' , l(805.0) ) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'cia_ren({})' , 0, l(20), 8) , (IW | AB, 'fast_nia_wen({})', 0, l(20), 8) , (IW | AB, 'msr_ren({})' , 0, l(20), 8) @@ -557,8 +557,8 @@ def scriptMain ( **kw ): cellInt = af.getCell( 'int', CRL.Catalog.State.Views ) blockInt = Block.create \ ( cellInt - , ioPins=[ (IN , 'clk' , l(805.0) ) - , (IW | AB, 'rst' , 0, l(20), 1) + , ioPins=[ (IN , 'coresync_clk' , l(805.0) ) + , (IW | AB, 'coresync_rst' , 0, l(20), 1) , (IW | AB, 'wen({})' , 0, l(20), 32) , (IW | AB, 'wen_1({})' , 0, l(20), 32) , (IW | AB, 'src1_ren({})' , 0, l(20), 32) -- 2.30.2