From 1704ba2273d9623095ddcd269055aedb8e818e03 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 17 Dec 2008 09:51:18 -0800 Subject: [PATCH] Make Alpha pseudo-insts available from SE mode. --- src/arch/alpha/isa/decoder.isa | 21 +++++++++++++----- src/arch/alpha/isa/main.isa | 2 -- src/cpu/BaseCPU.py | 9 ++++---- src/sim/SConscript | 2 +- src/sim/pseudo_inst.cc | 39 +++++++++++++++++++++++----------- src/sim/pseudo_inst.hh | 13 +++++++----- 6 files changed, 57 insertions(+), 29 deletions(-) diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 115cf7fa7..f057f00cc 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -783,14 +783,19 @@ decode OPCODE default Unknown::unknown() { } } - format BasicOperate { - 0x1e: decode PALMODE { - 0: OpcdecFault::hw_rei(); - 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); + 0x1e: decode PALMODE { + 0: OpcdecFault::hw_rei(); + format BasicOperate { + 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); } + } + +#endif + format BasicOperate { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { +#if FULL_SYSTEM 0x00: arm({{ PseudoInst::arm(xc->tcBase()); }}, IsNonSpeculative); @@ -806,6 +811,7 @@ decode OPCODE default Unknown::unknown() { 0x04: quiesceTime({{ R0 = PseudoInst::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); +#endif 0x07: rpns({{ R0 = PseudoInst::rpns(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); @@ -822,12 +828,14 @@ decode OPCODE default Unknown::unknown() { 0x21: m5exit({{ PseudoInst::m5exit(xc->tcBase(), R16); }}, No_OpClass, IsNonSpeculative); +#if FULL_SYSTEM 0x31: loadsymbol({{ PseudoInst::loadsymbol(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); +#endif 0x40: resetstats({{ PseudoInst::resetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); @@ -840,18 +848,22 @@ decode OPCODE default Unknown::unknown() { 0x43: m5checkpoint({{ PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); }}, IsNonSpeculative); +#if FULL_SYSTEM 0x50: m5readfile({{ R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); }}, IsNonSpeculative); +#endif 0x51: m5break({{ PseudoInst::debugbreak(xc->tcBase()); }}, IsNonSpeculative); 0x52: m5switchcpu({{ PseudoInst::switchcpu(xc->tcBase()); }}, IsNonSpeculative); +#if FULL_SYSTEM 0x53: m5addsymbol({{ PseudoInst::addsymbol(xc->tcBase(), R16, R17); }}, IsNonSpeculative); +#endif 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); }}, IsNonSpeculative); @@ -872,5 +884,4 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); } } -#endif } diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 5231712c8..f34bd4b33 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -68,9 +68,7 @@ using namespace AlphaISA; output exec {{ #include -#if FULL_SYSTEM #include "sim/pseudo_inst.hh" -#endif #include "arch/alpha/ipr.hh" #include "base/fenv.hh" #include "config/ss_compatible_fp.hh" diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index f98c6af8e..985c415a0 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -71,13 +71,14 @@ class BaseCPU(MemObject): checker = Param.BaseCPU("checker CPU") + do_checkpoint_insts = Param.Bool(True, + "enable checkpoint pseudo instructions") + do_statistics_insts = Param.Bool(True, + "enable statistics pseudo instructions") + if build_env['FULL_SYSTEM']: profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") - do_checkpoint_insts = Param.Bool(True, - "enable checkpoint pseudo instructions") - do_statistics_insts = Param.Bool(True, - "enable statistics pseudo instructions") else: workload = VectorParam.Process("processes to run") diff --git a/src/sim/SConscript b/src/sim/SConscript index 7acf4e9b6..48200161c 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -43,6 +43,7 @@ Source('eventq.cc') Source('faults.cc') Source('init.cc') BinSource('main.cc') +Source('pseudo_inst.cc') Source('root.cc') Source('serialize.cc') Source('sim_events.cc') @@ -54,7 +55,6 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('arguments.cc') - Source('pseudo_inst.cc') else: Source('tlb.cc') SimObject('Process.py') diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index e43279376..130a2f0fe 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -50,7 +50,9 @@ #include "sim/stats.hh" #include "sim/system.hh" #include "sim/debug.hh" +#if FULL_SYSTEM #include "sim/vptr.hh" +#endif using namespace std; @@ -59,6 +61,8 @@ using namespace TheISA; namespace PseudoInst { +#if FULL_SYSTEM + void arm(ThreadContext *tc) { @@ -125,6 +129,8 @@ quiesceTime(ThreadContext *tc) return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns; } +#endif + uint64_t rpns(ThreadContext *tc) { @@ -139,6 +145,8 @@ m5exit(ThreadContext *tc, Tick delay) mainEventQueue.schedule(event, when); } +#if FULL_SYSTEM + void loadsymbol(ThreadContext *tc) { @@ -187,6 +195,21 @@ loadsymbol(ThreadContext *tc) file.close(); } +void +addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) +{ + char symb[100]; + CopyStringOut(tc, symb, symbolAddr, 100); + std::string symbol(symb); + + DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); + + tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); +} + +#endif + + void resetstats(ThreadContext *tc, Tick delay, Tick period) { @@ -213,18 +236,6 @@ dumpstats(ThreadContext *tc, Tick delay, Tick period) Stats::StatEvent(true, false, when, repeat); } -void -addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) -{ - char symb[100]; - CopyStringOut(tc, symb, symbolAddr, 100); - std::string symbol(symb); - - DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); - - tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); -} - void dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { @@ -251,6 +262,8 @@ m5checkpoint(ThreadContext *tc, Tick delay, Tick period) mainEventQueue.schedule(event, when); } +#if FULL_SYSTEM + uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) { @@ -286,6 +299,8 @@ readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) return result; } +#endif + void debugbreak(ThreadContext *tc) { diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 80f58f80d..7d013eda7 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -42,22 +42,25 @@ extern bool doStatisticsInsts; extern bool doCheckpointInsts; extern bool doQuiesce; +#if FULL_SYSTEM void arm(ThreadContext *tc); void quiesce(ThreadContext *tc); void quiesceNs(ThreadContext *tc, uint64_t ns); void quiesceCycles(ThreadContext *tc, uint64_t cycles); uint64_t quiesceTime(ThreadContext *tc); +uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, + uint64_t offset); +void loadsymbol(ThreadContext *xc); +void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); +#endif + uint64_t rpns(ThreadContext *tc); void m5exit(ThreadContext *tc, Tick delay); -void loadsymbol(ThreadContext *xc); void resetstats(ThreadContext *tc, Tick delay, Tick period); void dumpstats(ThreadContext *tc, Tick delay, Tick period); void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); void m5checkpoint(ThreadContext *tc, Tick delay, Tick period); -uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, - uint64_t offset); void debugbreak(ThreadContext *tc); void switchcpu(ThreadContext *tc); -void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); -/* namespace PsuedoInst */ } +/* namespace PseudoInst */ } -- 2.30.2