From 1718fdc048570a34bf653958b6c3d40d75db4614 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 16 Dec 2020 13:16:49 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64.mdwn | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 77f0f0f88..2e89527a0 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -111,6 +111,13 @@ In the following table, `<N>` denotes the value of the corresponding register fi
 | 10       | Vector                 | `SVCR<N>_000` | `SV[F]R<N>_00`      |
 | 11       | Vector                 | `SVCR<N>_100` | `SV[F]R<N>_10`      |
 
+| R\*_EXTRA2 | Mode | CR Register   | Int/FP<br/>Register |
+|-----------|-------|---------------|---------------------|
+| 00       | Scalar | `` | `RA`                |
+| 01       | Scalar | `` | `RA || 0b00`      |
+| 10       | Vector | `` | `RA || 0b00`      |
+| 11       | Vector | `` | `RA || 0b10`   |
+
 ## ELWIDTH Encoding
 
 | Instruction Kind | ELWIDTH Value | Mnemonic                  | Description                                                                         |
-- 
2.30.2