From 172eee700ecddedbf9d66883d9cbb20cb13f0646 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Jun 2020 18:31:02 +0100 Subject: [PATCH] missing test.mem arg for ISA in test_core --- src/soc/simple/test/test_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index ace4b256..17742940 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -77,7 +77,7 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - sim = ISA(pdecode2, test.regs, test.sprs, test.cr) + sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) -- 2.30.2