From 174e0b00c1875420014bd7f32bffd5070f5d5cba Mon Sep 17 00:00:00 2001 From: Jiong Wang Date: Mon, 10 Oct 2016 13:50:10 +0000 Subject: [PATCH] [4/4] ARMv8.2-A testsuite for new scalar intrinsics gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: Support FMT64. * gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c: New. From-SVN: r240924 --- gcc/testsuite/ChangeLog | 62 ++++++++ .../advsimd-intrinsics/unary_scalar_op.inc | 1 + .../aarch64/advsimd-intrinsics/vabdh_f16_1.c | 44 ++++++ .../aarch64/advsimd-intrinsics/vcageh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcagth_f16_1.c | 21 +++ .../aarch64/advsimd-intrinsics/vcaleh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcalth_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vceqh_f16_1.c | 21 +++ .../aarch64/advsimd-intrinsics/vceqzh_f16_1.c | 21 +++ .../aarch64/advsimd-intrinsics/vcgeh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcgezh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcgth_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcgtzh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcleh_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vclezh_f16_1.c | 21 +++ .../aarch64/advsimd-intrinsics/vclth_f16_1.c | 22 +++ .../aarch64/advsimd-intrinsics/vcltzh_f16_1.c | 21 +++ .../advsimd-intrinsics/vcvtah_s16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtah_s64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtah_u16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtah_u64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvth_f16_s16_1.c | 25 +++ .../advsimd-intrinsics/vcvth_f16_s64_1.c | 25 +++ .../advsimd-intrinsics/vcvth_f16_u16_1.c | 25 +++ .../advsimd-intrinsics/vcvth_f16_u64_1.c | 25 +++ .../advsimd-intrinsics/vcvth_n_f16_s16_1.c | 46 ++++++ .../advsimd-intrinsics/vcvth_n_f16_s64_1.c | 46 ++++++ .../advsimd-intrinsics/vcvth_n_f16_u16_1.c | 46 ++++++ .../advsimd-intrinsics/vcvth_n_f16_u64_1.c | 46 ++++++ .../advsimd-intrinsics/vcvth_n_s16_f16_1.c | 29 ++++ .../advsimd-intrinsics/vcvth_n_s64_f16_1.c | 29 ++++ .../advsimd-intrinsics/vcvth_n_u16_f16_1.c | 29 ++++ .../advsimd-intrinsics/vcvth_n_u64_f16_1.c | 29 ++++ .../advsimd-intrinsics/vcvth_s16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvth_s64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvth_u16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvth_u64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtmh_s16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtmh_s64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtmh_u16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtmh_u64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtnh_s16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtnh_s64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtnh_u16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtnh_u64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtph_s16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtph_s64_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtph_u16_f16_1.c | 23 +++ .../advsimd-intrinsics/vcvtph_u64_f16_1.c | 23 +++ .../advsimd-intrinsics/vfmash_lane_f16_1.c | 143 ++++++++++++++++++ .../aarch64/advsimd-intrinsics/vmaxh_f16_1.c | 34 +++++ .../aarch64/advsimd-intrinsics/vminh_f16_1.c | 34 +++++ .../advsimd-intrinsics/vmulh_lane_f16_1.c | 90 +++++++++++ .../aarch64/advsimd-intrinsics/vmulxh_f16_1.c | 50 ++++++ .../advsimd-intrinsics/vmulxh_lane_f16_1.c | 91 +++++++++++ .../advsimd-intrinsics/vrecpeh_f16_1.c | 42 +++++ .../advsimd-intrinsics/vrecpsh_f16_1.c | 50 ++++++ .../advsimd-intrinsics/vrecpxh_f16_1.c | 32 ++++ .../advsimd-intrinsics/vrsqrteh_f16_1.c | 30 ++++ .../advsimd-intrinsics/vrsqrtsh_f16_1.c | 50 ++++++ 60 files changed, 1916 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e201cdc2126..20c7aec71ba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,65 @@ +2016-10-10 Jiong Wang + + * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: Support FMT64. + * gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c: New. + 2016-10-10 Jiong Wang * gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc index 86403d28ae6..66c89068f61 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc @@ -64,6 +64,7 @@ extern void abort (); /* Format strings for error reporting. */ #define FMT16 "0x%04x" #define FMT32 "0x%08x" +#define FMT64 "0x%016x" #define FMT CAT (FMT,OUTPUT_TYPE_SIZE) /* Type construction: forms TS_t, where T is the base type and S the size in diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c new file mode 100644 index 00000000000..3a5efa58088 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results. + Absolute difference between INPUT1 and INPUT2 in binary_scalar_op.inc. */ +uint16_t expected[] = +{ + 0x3C00, + 0x3C00, + 0x4654, + 0x560E, + 0x4900, + 0x36B8, + 0x419a, + 0x4848, + 0x3d34, + 0x4cec, + 0x4791, + 0x3f34, + 0x484d, + 0x4804, + 0x469c, + 0x4ceb, + 0x7c00, + 0x7c00 +}; + +#define TEST_MSG "VABDH_F16" +#define INSN_NAME vabdh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c new file mode 100644 index 00000000000..0bebec76248 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF}; + +#define TEST_MSG "VCAGEH_F16" +#define INSN_NAME vcageh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c new file mode 100644 index 00000000000..68ce599719e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0}; + +#define TEST_MSG "VCAGTH_F16" +#define INSN_NAME vcagth_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c new file mode 100644 index 00000000000..1b5a09b4629 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0, + 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0, + 0x0, 0xFFFF, 0xFFFF}; + +#define TEST_MSG "VCALEH_F16" +#define INSN_NAME vcaleh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c new file mode 100644 index 00000000000..766c783f3b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0, + 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0, + 0x0, 0x0, 0x0}; + +#define TEST_MSG "VCALTH_F16" +#define INSN_NAME vcalth_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c new file mode 100644 index 00000000000..8f5c14b4349 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + +#define TEST_MSG "VCEQH_F16" +#define INSN_NAME vceqh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c new file mode 100644 index 00000000000..ccfecf42999 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + +#define TEST_MSG "VCEQZH_F16" +#define INSN_NAME vceqzh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c new file mode 100644 index 00000000000..161c7a04e1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, + 0xFFFF, 0x0}; + +#define TEST_MSG "VCGEH_F16" +#define INSN_NAME vcgeh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c new file mode 100644 index 00000000000..2d3cd8ad56a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, + 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0x0, 0xFFFF, 0xFFFF, 0x0}; + +#define TEST_MSG "VCGEZH_F16" +#define INSN_NAME vcgezh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c new file mode 100644 index 00000000000..0d353859b4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, + 0xFFFF, 0x0}; + +#define TEST_MSG "VCGTH_F16" +#define INSN_NAME vcgth_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c new file mode 100644 index 00000000000..ca23e3f0013 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, + 0xFFFF, 0xFFFF, 0x0}; + +#define TEST_MSG "VCGTZH_F16" +#define INSN_NAME vcgtzh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c new file mode 100644 index 00000000000..f51cac35635 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, + 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0, + 0xFFFF}; + +#define TEST_MSG "VCLEH_F16" +#define INSN_NAME vcleh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c new file mode 100644 index 00000000000..57901c8bd45 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF}; + +#define TEST_MSG "VCLEZH_F16" +#define INSN_NAME vclezh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c new file mode 100644 index 00000000000..32188732deb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, + 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0, + 0xFFFF}; + +#define TEST_MSG "VCLTH_F16" +#define INSN_NAME vclth_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c new file mode 100644 index 00000000000..af6a5b64414 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF}; + +#define TEST_MSG "VCltZH_F16" +#define INSN_NAME vcltzh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c new file mode 100644 index 00000000000..2084c3038c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 }; + +#define TEST_MSG "VCVTAH_S16_F16" +#define INSN_NAME vcvtah_s16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c new file mode 100644 index 00000000000..a27871bbf2a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 }; + +#define TEST_MSG "VCVTAH_S64_F16" +#define INSN_NAME vcvtah_s64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c new file mode 100644 index 00000000000..0642ae037ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 }; + +#define TEST_MSG "VCVTAH_u16_F16" +#define INSN_NAME vcvtah_u16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c new file mode 100644 index 00000000000..2d197b4eab3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 }; + +#define TEST_MSG "VCVTAH_u64_F16" +#define INSN_NAME vcvtah_u64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c new file mode 100644 index 00000000000..540b637fbfe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +int16_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 }; +uint16_t expected[] = { 0x57B0 /* 123.0. */, 0xE06E /* -567.0. */, + 0x0000 /* 0.0. */, 0x6400 /* 1024. */, + 0xD3E0 /* -63. */, 0x5948 /* 169. */, + 0xC400 /* -4. */, 0x54D0 /* 77. */ }; + +#define TEST_MSG "VCVTH_F16_S16" +#define INSN_NAME vcvth_f16_s16 + +#define EXPECTED expected + +#define INPUT input +#define INPUT_TYPE int16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c new file mode 100644 index 00000000000..5f17dbe9cc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +int64_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 }; +uint16_t expected[] = { 0x57B0 /* 123.0. */, 0xE06E /* -567.0. */, + 0x0000 /* 0.0. */, 0x6400 /* 1024. */, + 0xD3E0 /* -63. */, 0x5948 /* 169. */, + 0xC400 /* -4. */, 0x54D0 /* 77. */ }; + +#define TEST_MSG "VCVTH_F16_S64" +#define INSN_NAME vcvth_f16_s64 + +#define EXPECTED expected + +#define INPUT input +#define INPUT_TYPE int64_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c new file mode 100644 index 00000000000..426700cef0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint16_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 }; +uint16_t expected[] = { 0x57B0 /* 123.0. */, 0x606E /* 567.0. */, + 0x0000 /* 0.0. */, 0x6400 /* 1024.0. */, + 0x53E0 /* 63.0. */, 0x5948 /* 169.0. */, + 0x4400 /* 4.0. */, 0x54D0 /* 77.0. */ }; + +#define TEST_MSG "VCVTH_F16_U16" +#define INSN_NAME vcvth_f16_u16 + +#define EXPECTED expected + +#define INPUT input +#define INPUT_TYPE uint16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c new file mode 100644 index 00000000000..3413de021a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +uint64_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 }; +uint16_t expected[] = { 0x57B0 /* 123.0. */, 0x606E /* 567.0. */, + 0x0000 /* 0.0. */, 0x6400 /* 1024.0. */, + 0x53E0 /* 63.0. */, 0x5948 /* 169.0. */, + 0x4400 /* 4.0. */, 0x54D0 /* 77.0. */ }; + +#define TEST_MSG "VCVTH_F16_U64" +#define INSN_NAME vcvth_f16_u64 + +#define EXPECTED expected + +#define INPUT input +#define INPUT_TYPE uint64_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c new file mode 100644 index 00000000000..25265d19e7a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +int16_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 }; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = { 0x3800 /* 0.5. */, + 0x4500 /* 5. */, + 0x4E00 /* 24. */, + 0x5240 /* 50. */, + 0xB800 /* -0.5. */, + 0xC500 /* -5. */, + 0x4300 /* 3.5. */, + 0xC300 /* -3.5. */ }; + +uint16_t expected_2[] = { 0x3400 /* 0.25. */, + 0x4100 /* 2.5. */, + 0x4A00 /* 12. */, + 0x4E40 /* 25. */, + 0xB400 /* -0.25. */, + 0xC100 /* -2.5. */, + 0x3F00 /* 1.75. */, + 0xBF00 /* -1.75. */ }; + +#define TEST_MSG "VCVTH_N_F16_S16" +#define INSN_NAME vcvth_n_f16_s16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE int16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c new file mode 100644 index 00000000000..f0adb097e8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +int64_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 }; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = { 0x3800 /* 0.5. */, + 0x4500 /* 5. */, + 0x4E00 /* 24. */, + 0x5240 /* 50. */, + 0xB800 /* -0.5. */, + 0xC500 /* -5. */, + 0x4300 /* 3.5. */, + 0xC300 /* -3.5. */ }; + +uint16_t expected_2[] = { 0x3400 /* 0.25. */, + 0x4100 /* 2.5. */, + 0x4A00 /* 12. */, + 0x4E40 /* 25. */, + 0xB400 /* -0.25. */, + 0xC100 /* -2.5. */, + 0x3F00 /* 1.75. */, + 0xBF00 /* -1.75. */ }; + +#define TEST_MSG "VCVTH_N_F16_S64" +#define INSN_NAME vcvth_n_f16_s64 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE int64_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c new file mode 100644 index 00000000000..74c4e60d50d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +uint16_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 }; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = { 0x3800 /* 0.5. */, + 0x4500 /* 5. */, + 0x4E00 /* 24. */, + 0x5240 /* 50. */, + 0x5FD0 /* 500. */, + 0x0000 /* 0.0. */, + 0x5BD0 /* 250. */, + 0x4480 /* 4.5. */ }; + +uint16_t expected_2[] = { 0x3400 /* 0.25. */, + 0x4100 /* 2.5. */, + 0x4A00 /* 12. */, + 0x4E40 /* 25. */, + 0x5BD0 /* 250. */, + 0x0000 /* 0.0. */, + 0x57D0 /* 125. */, + 0x4080 /* 2.25. */ }; + +#define TEST_MSG "VCVTH_N_F16_U16" +#define INSN_NAME vcvth_n_f16_u16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE uint16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c new file mode 100644 index 00000000000..b393767b356 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +uint64_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 }; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = { 0x3800 /* 0.5. */, + 0x4500 /* 5. */, + 0x4E00 /* 24. */, + 0x5240 /* 50. */, + 0x5FD0 /* 500. */, + 0x0000 /* 0.0. */, + 0x5BD0 /* 250. */, + 0x4480 /* 4.5. */ }; + +uint16_t expected_2[] = { 0x3400 /* 0.25. */, + 0x4100 /* 2.5. */, + 0x4A00 /* 12. */, + 0x4E40 /* 25. */, + 0x5BD0 /* 250. */, + 0x0000 /* 0.0. */, + 0x57D0 /* 125. */, + 0x4080 /* 2.25. */ }; + +#define TEST_MSG "VCVTH_N_F16_U64" +#define INSN_NAME vcvth_n_f16_u64 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE uint64_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c new file mode 100644 index 00000000000..247f7c9fe68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 }; +int16_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 }; +int16_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 }; + +#define TEST_MSG "VCVTH_N_S16_F16" +#define INSN_NAME vcvth_n_s16_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c new file mode 100644 index 00000000000..27502c220f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 }; +int64_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 }; +int64_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 }; + +#define TEST_MSG "VCVTH_N_S64_F16" +#define INSN_NAME vcvth_n_s64_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c new file mode 100644 index 00000000000..e5f57f12c6b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 }; +uint16_t expected_1[] = {5, 200, 14, 19, 10, 18, 9, 154}; +uint16_t expected_2[] = {10, 400, 28, 39, 20, 36, 19, 308}; + +#define TEST_MSG "VCVTH_N_U16_F16" +#define INSN_NAME vcvth_n_u16_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c new file mode 100644 index 00000000000..cfc33c24e64 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 }; +uint64_t expected_1[] = { 5, 200, 14, 19, 10, 18, 9, 154 }; +uint64_t expected_2[] = { 10, 400, 28, 39, 20, 36, 19, 308 }; + +#define TEST_MSG "VCVTH_N_U64_F16" +#define INSN_NAME vcvth_n_u64_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c new file mode 100644 index 00000000000..99656544533 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int16_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 }; + +#define TEST_MSG "VCVTH_S16_F16" +#define INSN_NAME vcvth_s16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c new file mode 100644 index 00000000000..c7b3d17469b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int64_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 }; + +#define TEST_MSG "VCVTH_S64_F16" +#define INSN_NAME vcvth_s64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c new file mode 100644 index 00000000000..e3c5d3a0b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 }; + +#define TEST_MSG "VCVTH_u16_F16" +#define INSN_NAME vcvth_u16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c new file mode 100644 index 00000000000..a904e5e472a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 }; + +#define TEST_MSG "VCVTH_u64_F16" +#define INSN_NAME vcvth_u64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c new file mode 100644 index 00000000000..ef0132a1ccd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int16_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 }; + +#define TEST_MSG "VCVTMH_S16_F16" +#define INSN_NAME vcvtmh_s16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c new file mode 100644 index 00000000000..7b5b16ff569 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int64_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 }; + +#define TEST_MSG "VCVTMH_S64_F16" +#define INSN_NAME vcvtmh_s64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c new file mode 100644 index 00000000000..db56171da3e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 }; + +#define TEST_MSG "VCVTMH_u16_F16" +#define INSN_NAME vcvtmh_u16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c new file mode 100644 index 00000000000..cae69a34704 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 }; + +#define TEST_MSG "VCVTMH_u64_F16" +#define INSN_NAME vcvtmh_u64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c new file mode 100644 index 00000000000..dec8d857036 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 }; + +#define TEST_MSG "VCVTNH_S16_F16" +#define INSN_NAME vcvtnh_s16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c new file mode 100644 index 00000000000..0048b5bf153 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 }; + +#define TEST_MSG "VCVTNH_S64_F16" +#define INSN_NAME vcvtnh_s64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c new file mode 100644 index 00000000000..0a95cea6352 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 }; + +#define TEST_MSG "VCVTNH_u16_F16" +#define INSN_NAME vcvtnh_u16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c new file mode 100644 index 00000000000..3b1b273b645 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 }; + +#define TEST_MSG "VCVTNH_u64_F16" +#define INSN_NAME vcvtnh_u64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c new file mode 100644 index 00000000000..5ff0d226077 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int16_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 }; + +#define TEST_MSG "VCVTPH_S16_F16" +#define INSN_NAME vcvtph_s16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c new file mode 100644 index 00000000000..290c5b13a7c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 }; +int64_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 }; + +#define TEST_MSG "VCVTPH_S64_F16" +#define INSN_NAME vcvtph_s64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c new file mode 100644 index 00000000000..e367dad8e5c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint16_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 }; + +#define TEST_MSG "VCVTPH_u16_F16" +#define INSN_NAME vcvtph_u16_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c new file mode 100644 index 00000000000..02290991a9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 }; +uint64_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 }; + +#define TEST_MSG "VCVTPH_u64_F16" +#define INSN_NAME vcvtph_u64_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint64_t +#define OUTPUT_TYPE_SIZE 64 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c new file mode 100644 index 00000000000..ea751da72b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c @@ -0,0 +1,143 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define FP16_C(a) ((__fp16) a) +#define A0 FP16_C (123.4) +#define B0 FP16_C (-5.8) +#define C0 FP16_C (-3.8) +#define D0 FP16_C (10) + +#define A1 FP16_C (12.4) +#define B1 FP16_C (-5.8) +#define C1 FP16_C (90.8) +#define D1 FP16_C (24) + +#define A2 FP16_C (23.4) +#define B2 FP16_C (-5.8) +#define C2 FP16_C (8.9) +#define D2 FP16_C (4) + +#define E0 FP16_C (3.4) +#define F0 FP16_C (-55.8) +#define G0 FP16_C (-31.8) +#define H0 FP16_C (2) + +#define E1 FP16_C (123.4) +#define F1 FP16_C (-5.8) +#define G1 FP16_C (-3.8) +#define H1 FP16_C (102) + +#define E2 FP16_C (4.9) +#define F2 FP16_C (-15.8) +#define G2 FP16_C (39.8) +#define H2 FP16_C (49) + +extern void abort (); + +float16_t src1[8] = { A0, B0, C0, D0, E0, F0, G0, H0 }; +float16_t src2[8] = { A1, B1, C1, D1, E1, F1, G1, H1 }; +VECT_VAR_DECL (src3, float, 16, 4) [] = { A2, B2, C2, D2 }; +VECT_VAR_DECL (src3, float, 16, 8) [] = { A2, B2, C2, D2, E2, F2, G2, H2 }; + +/* Expected results for vfmah_lane_f16. */ +uint16_t expected[4] = { 0x5E76 /* A0 + A1 * A2. */, + 0x4EF6 /* B0 + B1 * B2. */, + 0x6249 /* C0 + C1 * C2. */, + 0x56A0 /* D0 + D1 * D2. */ }; + +/* Expected results for vfmah_laneq_f16. */ +uint16_t expected_laneq[8] = { 0x5E76 /* A0 + A1 * A2. */, + 0x4EF6 /* B0 + B1 * B2. */, + 0x6249 /* C0 + C1 * C2. */, + 0x56A0 /* D0 + D1 * D2. */, + 0x60BF /* E0 + E1 * E2. */, + 0x507A /* F0 + F1 * F2. */, + 0xD9B9 /* G0 + G1 * G2. */, + 0x6CE2 /* H0 + H1 * H2. */ }; + +/* Expected results for vfmsh_lane_f16. */ +uint16_t expected_fms[4] = { 0xD937 /* A0 + -A1 * A2. */, + 0xD0EE /* B0 + -B1 * B2. */, + 0xE258 /* C0 + -C1 * C2. */, + 0xD560 /* D0 + -D1 * D2. */ }; + +/* Expected results for vfmsh_laneq_f16. */ +uint16_t expected_fms_laneq[8] = { 0xD937 /* A0 + -A1 * A2. */, + 0xD0EE /* B0 + -B1 * B2. */, + 0xE258 /* C0 + -C1 * C2. */, + 0xD560 /* D0 + -D1 * D2. */, + 0xE0B2 /* E0 + -E1 * E2. */, + 0xD89C /* F0 + -F1 * F2. */, + 0x5778 /* G0 + -G1 * G2. */, + 0xECE1 /* H0 + -H1 * H2. */ }; + +void exec_vfmash_lane_f16 (void) +{ +#define CHECK_LANE(N) \ + ret = vfmah_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\ + if (*(uint16_t *) &ret != expected[N])\ + abort (); + + DECL_VARIABLE(vsrc3, float, 16, 4); + VLOAD (vsrc3, src3, , float, f, 16, 4); + float16_t ret; + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + +#undef CHECK_LANE +#define CHECK_LANE(N) \ + ret = vfmah_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ + if (*(uint16_t *) &ret != expected_laneq[N]) \ + abort (); + + DECL_VARIABLE(vsrc3, float, 16, 8); + VLOAD (vsrc3, src3, q, float, f, 16, 8); + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + CHECK_LANE(4) + CHECK_LANE(5) + CHECK_LANE(6) + CHECK_LANE(7) + +#undef CHECK_LANE +#define CHECK_LANE(N) \ + ret = vfmsh_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\ + if (*(uint16_t *) &ret != expected_fms[N])\ + abort (); + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + +#undef CHECK_LANE +#define CHECK_LANE(N) \ + ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ + if (*(uint16_t *) &ret != expected_fms_laneq[N]) \ + abort (); + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + CHECK_LANE(4) + CHECK_LANE(5) + CHECK_LANE(6) + CHECK_LANE(7) +} + +int +main (void) +{ + exec_vfmash_lane_f16 (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c new file mode 100644 index 00000000000..182463ed74e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 123.4 +#define B -567.8 +#define C -34.8 +#define D 1024 +#define E 663.1 +#define F 169.1 +#define G -4.8 +#define H 77 + +float16_t input_1[] = { A, B, C, D }; +float16_t input_2[] = { E, F, G, H }; +float16_t expected[] = { E, F, G, D }; + +#define TEST_MSG "VMAXH_F16" +#define INSN_NAME vmaxh_f16 + +#define INPUT_1 input_1 +#define INPUT_2 input_2 +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c new file mode 100644 index 00000000000..d8efbcac693 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 123.4 +#define B -567.8 +#define C -34.8 +#define D 1024 +#define E 663.1 +#define F 169.1 +#define G -4.8 +#define H 77 + +float16_t input_1[] = { A, B, C, D }; +float16_t input_2[] = { E, F, G, H }; +float16_t expected[] = { A, B, C, H }; + +#define TEST_MSG "VMINH_F16" +#define INSN_NAME vminh_f16 + +#define INPUT_1 input_1 +#define INPUT_2 input_2 +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c new file mode 100644 index 00000000000..4cd5c37c632 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c @@ -0,0 +1,90 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define FP16_C(a) ((__fp16) a) +#define A FP16_C (13.4) +#define B FP16_C (-56.8) +#define C FP16_C (-34.8) +#define D FP16_C (12) +#define E FP16_C (63.1) +#define F FP16_C (19.1) +#define G FP16_C (-4.8) +#define H FP16_C (77) + +#define I FP16_C (0.7) +#define J FP16_C (-78) +#define K FP16_C (11.23) +#define L FP16_C (98) +#define M FP16_C (87.1) +#define N FP16_C (-8) +#define O FP16_C (-1.1) +#define P FP16_C (-9.7) + +extern void abort (); + +float16_t src1[8] = { A, B, C, D, I, J, K, L }; +VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H }; +VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P }; + +/* Expected results for vmulh_lane. */ +uint16_t expected[4] = { 0x629B /* A * E. */, 0xE43D /* B * F. */, + 0x5939 /* C * G. */, 0x6338 /* D * H. */ }; + + +/* Expected results for vmulh_lane. */ +uint16_t expected_laneq[8] = { 0x629B /* A * E. */, + 0xE43D /* B * F. */, + 0x5939 /* C * G. */, + 0x6338 /* D * H. */, + 0x53A0 /* I * M. */, + 0x60E0 /* J * N. */, + 0xCA2C /* K * O. */, + 0xE36E /* L * P. */ }; + +void exec_vmulh_lane_f16 (void) +{ +#define CHECK_LANE(N)\ + ret = vmulh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\ + if (*(uint16_t *) &ret != expected[N])\ + abort (); + + DECL_VARIABLE(vsrc2, float, 16, 4); + VLOAD (vsrc2, src2, , float, f, 16, 4); + float16_t ret; + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + +#undef CHECK_LANE +#define CHECK_LANE(N)\ + ret = vmulh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\ + if (*(uint16_t *) &ret != expected_laneq[N])\ + abort (); + + DECL_VARIABLE(vsrc2, float, 16, 8); + VLOAD (vsrc2, src2, q, float, f, 16, 8); + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + CHECK_LANE(4) + CHECK_LANE(5) + CHECK_LANE(6) + CHECK_LANE(7) +} + +int +main (void) +{ + exec_vmulh_lane_f16 (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c new file mode 100644 index 00000000000..66c744ce1c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 13.4 +#define B __builtin_inff () +#define C -34.8 +#define D -__builtin_inff () +#define E 63.1 +#define F 0.0 +#define G -4.8 +#define H 0.0 + +#define I 0.7 +#define J -__builtin_inff () +#define K 11.23 +#define L 98 +#define M 87.1 +#define N -0.0 +#define O -1.1 +#define P 7 + +float16_t input_1[] = { A, B, C, D, I, J, K, L }; +float16_t input_2[] = { E, F, G, H, M, N, O, P }; +uint16_t expected[] = { 0x629B /* A * E. */, + 0x4000 /* FP16_C (2.0f). */, + 0x5939 /* C * G. */, + 0xC000 /* FP16_C (-2.0f). */, + 0x53A0 /* I * M. */, + 0x4000 /* FP16_C (2.0f). */, + 0xCA2C /* K * O. */, + 0x615C /* L * P. */ }; + +#define TEST_MSG "VMULXH_F16" +#define INSN_NAME vmulxh_f16 + +#define INPUT_1 input_1 +#define INPUT_2 input_2 +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c new file mode 100644 index 00000000000..90a5be8de4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c @@ -0,0 +1,91 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define FP16_C(a) ((__fp16) a) +#define A FP16_C (13.4) +#define B FP16_C (__builtin_inff ()) +#define C FP16_C (-34.8) +#define D FP16_C (-__builtin_inff ()) +#define E FP16_C (63.1) +#define F FP16_C (0.0) +#define G FP16_C (-4.8) +#define H FP16_C (0.0) + +#define I FP16_C (0.7) +#define J FP16_C (-__builtin_inff ()) +#define K FP16_C (11.23) +#define L FP16_C (98) +#define M FP16_C (87.1) +#define N FP16_C (-0.0) +#define O FP16_C (-1.1) +#define P FP16_C (7) + +extern void abort (); + +float16_t src1[8] = { A, B, C, D, I, J, K, L }; +VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H }; +VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P }; + +/* Expected results for vmulxh_lane. */ +uint16_t expected[4] = { 0x629B /* A * E. */, + 0x4000 /* FP16_C (2.0f). */, + 0x5939 /* C * G. */, + 0xC000 /* FP16_C (-2.0f). */ }; + +/* Expected results for vmulxh_lane. */ +uint16_t expected_laneq[8] = { 0x629B /* A * E. */, + 0x4000 /* FP16_C (2.0f). */, + 0x5939 /* C * G. */, + 0xC000 /* FP16_C (-2.0f). */, + 0x53A0 /* I * M. */, + 0x4000 /* FP16_C (2.0f). */, + 0xCA2C /* K * O. */, + 0x615C /* L * P. */ }; + +void exec_vmulxh_lane_f16 (void) +{ +#define CHECK_LANE(N)\ + ret = vmulxh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\ + if (*(uint16_t *) &ret != expected[N])\ + abort (); + + DECL_VARIABLE(vsrc2, float, 16, 4); + VLOAD (vsrc2, src2, , float, f, 16, 4); + float16_t ret; + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + +#undef CHECK_LANE +#define CHECK_LANE(N)\ + ret = vmulxh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\ + if (*(uint16_t *) &ret != expected_laneq[N])\ + abort (); + + DECL_VARIABLE(vsrc2, float, 16, 8); + VLOAD (vsrc2, src2, q, float, f, 16, 8); + + CHECK_LANE(0) + CHECK_LANE(1) + CHECK_LANE(2) + CHECK_LANE(3) + CHECK_LANE(4) + CHECK_LANE(5) + CHECK_LANE(6) + CHECK_LANE(7) +} + +int +main (void) +{ + exec_vmulxh_lane_f16 (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c new file mode 100644 index 00000000000..3740d6afa68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 123.4 +#define B 567.8 +#define C 34.8 +#define D 1024 +#define E 663.1 +#define F 144.0 +#define G 4.8 +#define H 77 + +#define RECP_A 0x2028 /* 1/A. */ +#define RECP_B 0x1734 /* 1/B. */ +#define RECP_C 0x275C /* 1/C. */ +#define RECP_D 0x13FC /* 1/D. */ +#define RECP_E 0x162C /* 1/E. */ +#define RECP_F 0x1F18 /* 1/F. */ +#define RECP_G 0x32A8 /* 1/G. */ +#define RECP_H 0x22A4 /* 1/H. */ + +float16_t input[] = { A, B, C, D, E, F, G, H }; +uint16_t expected[] = { RECP_A, RECP_B, RECP_C, RECP_D, + RECP_E, RECP_F, RECP_G, RECP_H }; + +#define TEST_MSG "VRECPEH_F16" +#define INSN_NAME vrecpeh_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c new file mode 100644 index 00000000000..3e6b24e4378 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 12.4 +#define B -5.8 +#define C -3.8 +#define D 10 +#define E 66.1 +#define F 16.1 +#define G -4.8 +#define H -77 + +#define I 0.7 +#define J -78 +#define K 10.23 +#define L 98 +#define M 87 +#define N -87.81 +#define O -1.1 +#define P 47.8 + +float16_t input_1[] = { A, B, C, D, I, J, K, L }; +float16_t input_2[] = { E, F, G, H, M, N, O, P }; +uint16_t expected[] = { 0xE264 /* 2.0f - A * E. */, + 0x55F6 /* 2.0f - B * F. */, + 0xCC10 /* 2.0f - C * G. */, + 0x6208 /* 2.0f - D * H. */, + 0xD35D /* 2.0f - I * M. */, + 0xEEB0 /* 2.0f - J * N. */, + 0x4A9F /* 2.0f - K * O. */, + 0xEC93 /* 2.0f - L * P. */ }; + +#define TEST_MSG "VRECPSH_F16" +#define INSN_NAME vrecpsh_f16 + +#define INPUT_1 input_1 +#define INPUT_2 input_2 +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c new file mode 100644 index 00000000000..fc02b6b7760 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ + +float16_t input[] = { 123.4, 567.8, 34.8, 1024, 663.1, 144.0, 4.8, 77 }; +/* Expected results are calculated by: + for (index = 0; index < 8; index++) + { + uint16_t src_cast = * (uint16_t *) &src[index]; + * (uint16_t *) &expected[index] = + (src_cast & 0x8000) | (~src_cast & 0x7C00); + } */ +uint16_t expected[8] = { 0x2800, 0x1C00, 0x2C00, 0x1800, + 0x1C00, 0x2400, 0x3800, 0x2800 }; + +#define TEST_MSG "VRECPXH_F16" +#define INSN_NAME vrecpxh_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c new file mode 100644 index 00000000000..7c0e6195be6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +float16_t input[] = { 123.4, 67.8, 34.8, 24.0, 66.1, 144.0, 4.8, 77.0 }; +uint16_t expected[] = { 0x2DC4 /* FP16_C (1/__builtin_sqrtf (123.4)). */, + 0x2FC8 /* FP16_C (1/__builtin_sqrtf (67.8)). */, + 0x316C /* FP16_C (1/__builtin_sqrtf (34.8)). */, + 0x3288 /* FP16_C (1/__builtin_sqrtf (24.0)). */, + 0x2FDC /* FP16_C (1/__builtin_sqrtf (66.1)). */, + 0x2D54 /* FP16_C (1/__builtin_sqrtf (144.0)). */, + 0x3750 /* FP16_C (1/__builtin_sqrtf (4.8)). */, + 0x2F48 /* FP16_C (1/__builtin_sqrtf (77.0)). */ }; + +#define TEST_MSG "VRSQRTEH_F16" +#define INSN_NAME vrsqrteh_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c new file mode 100644 index 00000000000..a9753a4df06 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +#include + +/* Input values. */ +#define A 12.4 +#define B -5.8 +#define C -3.8 +#define D 10 +#define E 66.1 +#define F 16.1 +#define G -4.8 +#define H -77 + +#define I 0.7 +#define J -78 +#define K 10.23 +#define L 98 +#define M 87 +#define N -87.81 +#define O -1.1 +#define P 47.8 + +float16_t input_1[] = { A, B, C, D, I, J, K, L }; +float16_t input_2[] = { E, F, G, H, M, N, O, P }; +uint16_t expected[] = { 0xDE62 /* (3.0f + (-A) * E) / 2.0f. */, + 0x5206 /* (3.0f + (-B) * F) / 2.0f. */, + 0xC7A0 /* (3.0f + (-C) * G) / 2.0f. */, + 0x5E0A /* (3.0f + (-D) * H) / 2.0f. */, + 0xCF3D /* (3.0f + (-I) * M) / 2.0f. */, + 0xEAB0 /* (3.0f + (-J) * N) / 2.0f. */, + 0x471F /* (3.0f + (-K) * O) / 2.0f. */, + 0xE893 /* (3.0f + (-L) * P) / 2.0f. */ }; + +#define TEST_MSG "VRSQRTSH_F16" +#define INSN_NAME vrsqrtsh_f16 + +#define INPUT_1 input_1 +#define INPUT_2 input_2 +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "binary_scalar_op.inc" -- 2.30.2