From 1765baa4d77985ac39a9503ddf833c4b7ee644e0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 Apr 2022 10:50:33 +0100 Subject: [PATCH] connect (new) reset signal on IOPads which comes from the nmigen Pin. this had to be done because otherwise the IOPads are unstable. next experiment is to hook ResetSignal(dramsync) with the firmware-driven reset, which should allow the IOpads - and DQS - to fully stabilise (oh, and also allow retries on setting them up) --- gram/phy/ecp5ddrphy.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index e6e0fb1..d7d68b4 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -224,6 +224,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): # Clock -------------------------------------------------------------------------------- m.d.comb += [ self.pads.clk.o_clk.eq(ClockSignal("dramsync")), + self.pads.clk.o_prst.eq(ResetSignal("dramsync")), self.pads.clk.o_fclk.eq(ClockSignal("dramsync2x")), ] for i in range(len(self.pads.clk.o0)): @@ -237,6 +238,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): # Addresses and Commands --------------------------------------------------------------- m.d.comb += [ self.pads.a.o_clk.eq(ClockSignal("dramsync")), + self.pads.a.o_prst.eq(ResetSignal("dramsync")), self.pads.a.o_fclk.eq(ClockSignal("dramsync2x")), self.pads.ba.o_clk.eq(ClockSignal("dramsync")), self.pads.ba.o_fclk.eq(ClockSignal("dramsync2x")), @@ -278,6 +280,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): else: m.d.comb += [ pad.o_clk.eq(ClockSignal("dramsync")), + pad.o_prst.eq(ResetSignal("dramsync")), pad.o_fclk.eq(ClockSignal("dramsync2x")), ] if name == "reset": -- 2.30.2