From 176b9240a953e650aebc03f6fec3e82b6db7f04f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 Apr 2015 23:52:34 +0800 Subject: [PATCH] soc: use new ModuleTransformer API --- misoclib/soc/sdram.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 3a8c5617..2097c54e 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -61,7 +61,7 @@ class SDRAMSoC(SoC): from mibuild.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE - self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())) + self.submodules.wishbone2lasmi = FullMemoryWE()(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())) else: self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()) self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size) -- 2.30.2