From 17768bb7b428f367e351bf9bfa480bd0d4e57442 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 29 Nov 2012 17:52:31 -0800 Subject: [PATCH] i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL. v2: Use stencil->_WriteEnabled instead of setting GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric). v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff. The field is only 8-bits, so we'd trip the new SET_FIELD assertion when core Mesa gave us a value like 0xFFFFFFFF. The Gen7 code uses structure field widths to implicitly do this truncation. Fixes Piglit tests. v4: Use uint32_t for dw1/dw2, not uint8_t. Worst. Typo. Ever. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt [v2] --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_defines.h | 26 +++++ src/mesa/drivers/dri/i965/brw_state.h | 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- .../drivers/dri/i965/gen8_wm_depth_stencil.c | 102 ++++++++++++++++++ 5 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 318da0da177..ecee9edb3ba 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -147,4 +147,5 @@ i965_FILES = \ gen8_instruction.c \ gen8_sf_state.c \ gen8_vec4_generator.cpp \ + gen8_wm_depth_stencil.cpp \ $() diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 55f3da94c4a..56af37aaf5c 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1673,6 +1673,32 @@ enum brw_message_target { # define GEN8_RASTER_SCISSOR_ENABLE (1 << 1) # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0) +#define _3DSTATE_WM_DEPTH_STENCIL 0x784E /* GEN8+ */ +/* DW1 */ +# define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT 29 +# define GEN8_WM_DS_Z_FAIL_OP_SHIFT 26 +# define GEN8_WM_DS_Z_PASS_OP_SHIFT 23 +# define GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT 20 +# define GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT 17 +# define GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT 14 +# define GEN8_WM_DS_BF_Z_PASS_OP_SHIFT 11 +# define GEN8_WM_DS_STENCIL_FUNC_SHIFT 8 +# define GEN8_WM_DS_DEPTH_FUNC_SHIFT 5 +# define GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE (1 << 4) +# define GEN8_WM_DS_STENCIL_TEST_ENABLE (1 << 3) +# define GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE (1 << 2) +# define GEN8_WM_DS_DEPTH_TEST_ENABLE (1 << 1) +# define GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE (1 << 0) +/* DW2 */ +# define GEN8_WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24) +# define GEN8_WM_DS_STENCIL_TEST_MASK_SHIFT 24 +# define GEN8_WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16) +# define GEN8_WM_DS_STENCIL_WRITE_MASK_SHIFT 16 +# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8) +# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8 +# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0) +# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0 + enum brw_wm_barycentric_interp_mode { BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC = 0, BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC = 1, diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index cd23da02a79..748db535a11 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -131,6 +131,7 @@ extern const struct brw_tracked_state gen7_urb; extern const struct brw_tracked_state gen7_vs_state; extern const struct brw_tracked_state gen7_wm_state; extern const struct brw_tracked_state haswell_cut_index; +extern const struct brw_tracked_state gen8_wm_depth_stencil; extern const struct brw_tracked_state gen8_raster_state; extern const struct brw_tracked_state gen8_sbe_state; extern const struct brw_tracked_state gen8_sf_state; diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 0786c857970..5aceffcc114 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -268,7 +268,6 @@ static const struct brw_tracked_state *gen8_atoms[] = &gen7_urb, &gen6_blend_state, &gen6_color_calc_state, - &gen6_depth_stencil_state, &gen6_vs_push_constants, /* Before vs_state */ &gen7_gs_push_constants, /* Before gs_state */ @@ -305,6 +304,7 @@ static const struct brw_tracked_state *gen8_atoms[] = &gen8_raster_state, &gen8_sbe_state, &gen8_sf_state, + &gen8_wm_depth_stencil, &gen7_wm_state, &gen7_ps_state, diff --git a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c new file mode 100644 index 00000000000..8f5728f8ef9 --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c @@ -0,0 +1,102 @@ +/* + * Copyright © 2012 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "intel_batchbuffer.h" +#include "intel_fbo.h" +#include "brw_context.h" +#include "brw_defines.h" +#include "brw_state.h" + +static void +gen8_upload_wm_depth_stencil(struct brw_context *brw) +{ + struct gl_context *ctx = &brw->ctx; + uint32_t dw1 = 0, dw2 = 0; + + /* _NEW_BUFFERS */ + struct intel_renderbuffer *depth_irb = + intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); + + struct gl_stencil_attrib *stencil = &ctx->Stencil; + + /* _NEW_STENCIL | _NEW_BUFFERS */ + if (stencil->_Enabled) { + #define FUNC intel_translate_compare_func + #define OP intel_translate_stencil_op + + dw1 |= + GEN8_WM_DS_STENCIL_TEST_ENABLE | + FUNC(stencil->Function[0]) << GEN8_WM_DS_STENCIL_FUNC_SHIFT | + OP(stencil->FailFunc[0]) << GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT | + OP(stencil->ZFailFunc[0]) << GEN8_WM_DS_Z_FAIL_OP_SHIFT | + OP(stencil->ZPassFunc[0]) << GEN8_WM_DS_Z_PASS_OP_SHIFT; + + if (stencil->_WriteEnabled) + dw1 |= GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE; + + dw2 |= + SET_FIELD(stencil->WriteMask[0] & 0xff, GEN8_WM_DS_STENCIL_WRITE_MASK) | + SET_FIELD(stencil->ValueMask[0] & 0xff, GEN8_WM_DS_STENCIL_TEST_MASK); + + if (stencil->_TestTwoSide) { + const int b = stencil->_BackFace; + + dw1 |= + GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE | + FUNC(stencil->Function[b]) << GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT | + OP(stencil->FailFunc[b]) << GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT | + OP(stencil->ZFailFunc[b]) << GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT | + OP(stencil->ZPassFunc[b]) << GEN8_WM_DS_BF_Z_PASS_OP_SHIFT; + + dw2 |= SET_FIELD(stencil->WriteMask[b] & 0xff, + GEN8_WM_DS_BF_STENCIL_WRITE_MASK) | + SET_FIELD(stencil->ValueMask[b] & 0xff, + GEN8_WM_DS_BF_STENCIL_TEST_MASK); + } + } + + /* _NEW_DEPTH */ + if (ctx->Depth.Test && depth_irb) { + dw1 |= + GEN8_WM_DS_DEPTH_TEST_ENABLE | + FUNC(ctx->Depth.Func) << GEN8_WM_DS_DEPTH_FUNC_SHIFT; + + if (ctx->Depth.Mask) + dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE; + } + + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (3 - 2)); + OUT_BATCH(dw1); + OUT_BATCH(dw2); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen8_wm_depth_stencil = { + .dirty = { + .mesa = _NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL, + .brw = BRW_NEW_CONTEXT, + .cache = 0, + }, + .emit = gen8_upload_wm_depth_stencil, +}; -- 2.30.2