From 178f20c18c1fac572261be85dcc2e8412129e92f Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 26 Oct 2020 10:58:08 +0000
Subject: [PATCH]

---
 openpower/sv/predication.mdwn | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index 12ebc4823..23a06bb6a 100644
--- a/openpower/sv/predication.mdwn
+++ b/openpower/sv/predication.mdwn
@@ -15,6 +15,12 @@
 * must be easily implementable in any  microarchitecture including out-of-order 
 * must not compromise or penalise any microarchitectural performance
 * must cover up to 64 elements
+* must still work for elwidth over-rides
+
+# Capabilities
+
+* two modes, "zeroing" and "non-zeroing". zeroing mode places a zero in the masked-out element results, where non-zeroing leaves the destination (result) element unmodified.
+* predicate must be invertable via an opcode bit (to avoid the need for an instruction which inverts all bits of the predicate mask)
 
 # Proposals
 
-- 
2.30.2