From 17ab6614b27c898c570631ed286c9b37759c5167 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 16 Jun 2021 20:29:54 +0100 Subject: [PATCH] sorted out order of FPMULADD32 helper, only have rounding errors now --- src/openpower/decoder/helpers.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py index 134ef84a..3549516a 100644 --- a/src/openpower/decoder/helpers.py +++ b/src/openpower/decoder/helpers.py @@ -289,7 +289,7 @@ def FPMUL32(FRA, FRB): return cvt -def FPMULADD32(FRA, FRC, FRB, addsign, mulsign): +def FPMULADD32(FRA, FRC, FRB, mulsign, addsign): from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE #return FPMUL64(FRA, FRB) #FRA = DOUBLE(SINGLE(FRA)) @@ -298,12 +298,12 @@ def FPMULADD32(FRA, FRC, FRB, addsign, mulsign): if mulsign == 1: result = float(FRA) * float(FRC) + float(FRB) # fmadds elif mulsign == -1: - result = -(float(FRA) * float(FRC) + float(FRB)) # fnmadds + result = -(float(FRA) * float(FRC) - float(FRB)) # fnmsubs elif addsign == -1: if mulsign == 1: result = float(FRA) * float(FRC) - float(FRB) # fmsubs elif mulsign == -1: - result = -(float(FRA) * float(FRC) - float(FRB)) # fnmsubs + result = -(float(FRA) * float(FRC) + float(FRB)) # fnmadds elif addsign == 0: result = 0.0 log ("FPMULADD32", FRA, FRB, FRC, -- 2.30.2