From 17b6164cd9a168d5e3f4871a374f15c28628ebef Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Apr 2019 11:21:55 +0200 Subject: [PATCH] boards/platforms/sp605: apply same simplifications than on others platforms --- litex/boards/platforms/sp605.py | 40 ++++++++++++--------------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/litex/boards/platforms/sp605.py b/litex/boards/platforms/sp605.py index 655d9232..e8b26f43 100644 --- a/litex/boards/platforms/sp605.py +++ b/litex/boards/platforms/sp605.py @@ -1,22 +1,22 @@ # This file is Copyright (c) 2019 Michael Betz # License: BSD -from litex.build.generic_platform import Pins, IOStandard, Subsignal -from litex.build.xilinx import XilinxPlatform, XC3SProg, iMPACT +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, iMPACT _io = [ - # 4 LEDs above PCIE finger - ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")), # DS3 - ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")), # DS4 - ("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")), # DS5 - ("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")), # DS6 - ("user_led", 4, Pins("V19"), IOStandard("LVCMOS25")), # DS7 (FPGA_AWAKE) + ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")), + ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")), + ("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")), + ("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")), ("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")), ("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")), ("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")), ("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")), + ("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")), + ("serial", 0, Subsignal("cts", Pins("F19")), Subsignal("rts", Pins("F18")), @@ -24,11 +24,13 @@ _io = [ Subsignal("rx", Pins("H17")), IOStandard("LVCMOS25") ), + ("clk200", 0, Subsignal("p", Pins("K21")), Subsignal("n", Pins("K22")), IOStandard("LVDS_25") ), + ("eth_clocks", 0, # Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode Subsignal("gtx", Pins("AB7")), @@ -148,28 +150,14 @@ _connectors = [ "P": "C11", "N": "D11" }), - ] - class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 5.0 - def __init__(self, toolchain="ise"): - XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, - toolchain=toolchain) - # self.toolchain.bitstream_commands = \ - # ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] - # self.toolchain.additional_commands = \ - # ["write_cfgmem -force -format bin -interface spix4 -size 16 " - # "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise") - def create_programmer(self, programmer="xc3sprog"): - if programmer == "xc3sprog": - return XC3SProg("xpc", p=1) - elif programmer == "impact": - return iMPACT() - else: - raise ValueError("{} programmer is not supported" - .format(programmer)) + def create_programmer(self): + return iMPACT() -- 2.30.2