From 17e412a223a627e52299560ade70233b09ecff58 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 10 May 2021 18:01:01 +0100 Subject: [PATCH] testing load misaligned --- src/openpower/decoder/isa/caller.py | 2 +- .../decoder/isa/test_caller_ldst_exceptions.py | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 3526643e..9ce9905b 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -806,7 +806,7 @@ class ISACaller: raise e # ... re-raise # run a Trap but set DAR first print ("memory unaligned exception, DAR", e.dar) - self.spr['DAR'] = e.dar + self.spr['DAR'] = SelectableInt(e.dar, 64) self.call_trap(0x600, PIb.PRIV) # 0x600, privileged return diff --git a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py index 409b1957..2103f1ec 100644 --- a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py +++ b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py @@ -76,10 +76,11 @@ class DecoderTestCase(FHDLTestCase): def test_load_misalign(self): lst = ["addi 2, 0, 0x0010", # get PC off of zero - "ldx 3, 1, 0", + "ldx 3, 0, 1", ] initial_regs = [0] * 32 - initial_regs[1] = 0xFFFFFFFFFFFFFFFF # deliberately misaligned + all1s = 0xFFFFFFFFFFFFFFFF + initial_regs[1] = all1s initial_regs[2] = 0x0008 initial_mem = {0x0000: (0x5432123412345678, 8), 0x0008: (0xabcdef0187654321, 8), @@ -88,9 +89,10 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, initial_mem) - self.assertEqual(sim.gpr(1), SelectableInt(-1, 64)) + self.assertEqual(sim.gpr(1), SelectableInt(all1s, 64)) self.assertEqual(sim.gpr(3), SelectableInt(0, 64)) - self.assertEqual(sim.spr['DAR'], SelectableInt(-1, 64)) + print ("DAR", hex(sim.spr['DAR'].value)) + self.assertEqual(sim.spr['DAR'], all1s) def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None): simulator = run_tst(prog, initial_regs, mem=initial_mem) -- 2.30.2