From 17e6a214fd425cc5a10f1e6a1cbc794ca7f3be8a Mon Sep 17 00:00:00 2001 From: Topi Pohjolainen Date: Thu, 15 Sep 2016 08:22:34 +0300 Subject: [PATCH] i965: Provide slice details to renderbuffer fast clear state tracker This patch also introduces getter and setter for fast clear state preparing for tracking the state per slice. Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp.c | 3 +- src/mesa/drivers/dri/i965/brw_draw.c | 10 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 +++++++++++++++++++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 25 +++++----- 4 files changed, 68 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 74ff7fd2fc7..bdc36fabdb1 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -222,7 +222,8 @@ blorp_surf_for_miptree(struct brw_context *brw, } if (is_render_target) - intel_miptree_used_for_rendering(brw, mt); + intel_miptree_used_for_rendering(brw, mt, *level, + start_layer, num_layers); if (surf->aux_usage != ISL_AUX_USAGE_NONE) { /* We only really need a clear color if we also have an auxiliary diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 08a9fbc999e..0e0bc2700f5 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -386,10 +386,12 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) struct intel_renderbuffer *irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); - if (irb) { - brw_render_cache_set_add_bo(brw, irb->mt->bo); - intel_miptree_used_for_rendering(brw, irb->mt); - } + if (!irb) + continue; + + brw_render_cache_set_add_bo(brw, irb->mt->bo); + intel_miptree_used_for_rendering( + brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count); } } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 616bddb852e..62d28d29474 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2205,6 +2205,13 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw, BLORP_HIZ_OP_DEPTH_RESOLVE); } +enum intel_fast_clear_state +intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt, + unsigned level, unsigned layer) +{ + return mt->fast_clear_state; +} + static void intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt, unsigned level, unsigned layer) @@ -2226,6 +2233,45 @@ intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt, (void)layer; } +void +intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt, + unsigned level, + unsigned first_layer, + unsigned num_layers, + enum intel_fast_clear_state new_state) +{ + intel_miptree_check_color_resolve(mt, level, first_layer); + + assert(first_layer + num_layers <= mt->physical_depth0); + + mt->fast_clear_state = new_state; +} + +void +intel_miptree_used_for_rendering(const struct brw_context *brw, + struct intel_mipmap_tree *mt, unsigned level, + unsigned start_layer, unsigned num_layers) +{ + const bool is_lossless_compressed = + intel_miptree_is_lossless_compressed(brw, mt); + + for (unsigned i = 0; i < num_layers; ++i) { + const enum intel_fast_clear_state fast_clear_state = + intel_miptree_get_fast_clear_state(mt, level, start_layer + i); + + /* If the buffer was previously in fast clear state, change it to + * unresolved state, since it won't be guaranteed to be clear after + * rendering occurs. + */ + if (is_lossless_compressed || + fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR) { + intel_miptree_set_fast_clear_state( + mt, level, start_layer + i, 1, + INTEL_FAST_CLEAR_STATE_UNRESOLVED); + } + } +} + bool intel_miptree_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, unsigned level, diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 81483f54a6b..13de820f403 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -962,22 +962,25 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw, /**\}*/ +enum intel_fast_clear_state +intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt, + unsigned level, unsigned layer); + +void +intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt, + unsigned level, + unsigned first_layer, + unsigned num_layers, + enum intel_fast_clear_state new_state); + /** * Update the fast clear state for a miptree to indicate that it has been used * for rendering. */ -static inline void +void intel_miptree_used_for_rendering(const struct brw_context *brw, - struct intel_mipmap_tree *mt) -{ - /* If the buffer was previously in fast clear state, change it to - * unresolved state, since it won't be guaranteed to be clear after - * rendering occurs. - */ - if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR || - intel_miptree_is_lossless_compressed(brw, mt)) - mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED; -} + struct intel_mipmap_tree *mt, unsigned level, + unsigned start_layer, unsigned num_layers); /** * Flag values telling color resolve pass which special types of buffers -- 2.30.2