From 17f9fb615f1721f99cc7fef18d539152fed1e10a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 19 Apr 2023 12:04:22 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls012.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 956158b84..b7738b6cd 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -580,8 +580,8 @@ just stall straight away. Less extreme examples include instructions that take only a few cycles to complete, but if commonly used in tight loops with Conditional Branches, an Out-of-Order system with Speculative capability may need significantly -more Reservation Stations to hold in-flight data for instructions which -take longer than those which do not, so even a single clock cycle reduction +more Reservation Stations to hold in-flight data for *all* instructions when +some take longer, so even a single clock cycle reduction could become important. A rule of thumb is that in Hardware, at 4.8 ghz the budget for what is called -- 2.30.2