From 180912a7a30cd9253b5f28672aad315f253f35d6 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 20 Dec 2018 10:33:32 +0100
Subject: [PATCH] build/sim: handle verilog $finish and if coverage is enabled,
 write report at the end of the simulation.

---
 litex/build/sim/core/sim.c     | 10 +++++++---
 litex/build/sim/core/veril.cpp | 11 +++++++++++
 litex/build/sim/core/veril.h   |  8 ++++++++
 litex/build/sim/verilator.py   |  5 +++--
 4 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/litex/build/sim/core/sim.c b/litex/build/sim/core/sim.c
index 0ab18516..6e62c5cf 100644
--- a/litex/build/sim/core/sim.c
+++ b/litex/build/sim/core/sim.c
@@ -32,6 +32,7 @@ struct session_list_s {
 };
 
 struct session_list_s *sesslist=NULL;
+struct event_base *base=NULL;
 
 static int litex_sim_initialize_all(void **dut, void *base)
 {
@@ -175,7 +176,6 @@ static void cb(int sock, short which, void *arg)
   tv.tv_usec = 0;
   int i;
 
-
   for(i = 0; i < 1000; i++)
   {
     for(s = sesslist; s; s=s->next)
@@ -192,6 +192,9 @@ static void cb(int sock, short which, void *arg)
     }
   }
 
+  if (litex_sim_got_finish())
+    event_base_loopbreak(base);
+
   if (!evtimer_pending(ev, NULL)) {
     event_del(ev);
     evtimer_add(ev, &tv);
@@ -201,7 +204,6 @@ static void cb(int sock, short which, void *arg)
 int main()
 {
   void *vdut=NULL;
-  struct event_base *base=NULL;
   struct timeval tv;
 
   int ret;
@@ -235,8 +237,10 @@ int main()
   tv.tv_usec = 0;
   ev = event_new(base, -1, EV_PERSIST, cb, vdut);
   event_add(ev, &tv);
-
   event_base_dispatch(base);
+#if VM_COVERAGE
+  litex_sim_coverage_dump();
+#endif
 out:
   return ret;
 }
diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index cf5db23b..ef43fb1d 100644
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -32,6 +32,17 @@ extern "C" void litex_sim_tracer_dump()
   tfp->dump(ticks++);
 }
 
+extern "C" int litex_sim_got_finish()
+{
+  return Verilated::gotFinish();
+}
+
+#if VM_COVERAGE
+extern "C" void litex_sim_coverage_dump()
+{
+  VerilatedCov::write("dut.cov");
+}
+#endif
 
 vluint64_t main_time = 0;
 double sc_time_stamp()
diff --git a/litex/build/sim/core/veril.h b/litex/build/sim/core/veril.h
index b780793b..35326ade 100644
--- a/litex/build/sim/core/veril.h
+++ b/litex/build/sim/core/veril.h
@@ -7,10 +7,18 @@
 extern "C" void litex_sim_eval(void *vdut);
 extern "C" void litex_sim_init_tracer(void *vdut);
 extern "C" void litex_sim_tracer_dump();
+extern "C" int litex_sim_got_finish();
+#if VM_COVERAGE
+extern "C" void litex_sim_coverage_dump();
+#endif
 #else
 void litex_sim_eval(void *vdut);
 void litex_sim_init_tracer(void *vdut);
 void litex_sim_tracer_dump();
+int litex_sim_got_finish();
+#if VM_COVERAGE
+void litex_sim_coverage_dump();
+#endif
 #endif
 
 #endif
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 0d3c63f2..76f607f0 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -160,8 +160,9 @@ def _run_sim(build_name, as_root=False):
         if r != 0:
             raise OSError("Subprocess failed")
     except:
-        if sys.platform != "win32":
-            termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)
+        pass
+    if sys.platform != "win32":
+        termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)
 
 
 class SimVerilatorToolchain:
-- 
2.30.2