From 1812067b2df9981d115029cd429247bb76036466 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Thu, 26 Mar 2020 13:27:06 +0100 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- 35/0e8d427fd0608ba1f704f320334a965c15ec02 | 99 +++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 35/0e8d427fd0608ba1f704f320334a965c15ec02 diff --git a/35/0e8d427fd0608ba1f704f320334a965c15ec02 b/35/0e8d427fd0608ba1f704f320334a965c15ec02 new file mode 100644 index 0000000..f3a1362 --- /dev/null +++ b/35/0e8d427fd0608ba1f704f320334a965c15ec02 @@ -0,0 +1,99 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 12:27:13 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHRbN-0005wg-45; Thu, 26 Mar 2020 12:27:13 +0000 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jHRbL-0005wa-SG + for libre-riscv-dev@lists.libre-riscv.org; Thu, 26 Mar 2020 12:27:11 +0000 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 9A11D11C05B7 + for ; + Thu, 26 Mar 2020 13:27:11 +0100 (CET) +Message-ID: +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Thu, 26 Mar 2020 13:27:06 +0100 +In-Reply-To: +References: + <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> + + <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] cache SRAM organisation +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============3409687929976334724==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============3409687929976334724== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-ihFdX3VmdcrRvVu0ChtQ" + + +--=-ihFdX3VmdcrRvVu0ChtQ +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op wo 25-03-2020 om 15:53 [+0000]: +> On Wed, Mar 25, 2020 at 1:46 PM Staf Verhaegen wrote= +: +> a workaround (fallback position) is, we use DFF latches. i created a"byp= +ass latch" function which creates DFF latches with such acombinatorial bypa= +ss: we actually use them quite a lot (includingbetween pipeline stages so t= +hat we can programmatically cut the numberof pipeline stages in half at the= + flick of a switch). + +Would like to make separate side remark here. In ASICs MUXes are relative e= +xpensive gates with respect to delay and power. So if this principle is gen= +erally applied over the whole design it will make it difficult to make a ch= +ip that is competitive in power/performance compared to ARM/x86 CPUs. +In general if you are trying to optimize power/performance of your chip the= + KISS (keep it simple stupid) is your friend. In that respect your complex = +dual ISA decoder will have a power cost. + +greets, +Staf. + + + +--=-ihFdX3VmdcrRvVu0ChtQ-- + + + +--===============3409687929976334724== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============3409687929976334724==-- + + + -- 2.30.2