From 18212a85d7041e589ce5cd722571691985cd8426 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Sep 2020 22:59:19 +0100 Subject: [PATCH] cs_n and cke in sdram need to match in length --- src/soc/litex/florent/libresoc/ls180.py | 4 ++-- src/soc/litex/florent/ls180pins.txt | 6 +++--- src/soc/litex/florent/ls180soc.py | 17 ++++++++++------- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index e3969641..51d3654e 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -106,8 +106,8 @@ _io = [ Subsignal("we_n", Pins("T20")), Subsignal("ras_n", Pins("R20")), Subsignal("cas_n", Pins("T19")), - Subsignal("cs_n", Pins("P20 P30 P31 P32")), - Subsignal("cke", Pins("F20")), + Subsignal("cs_n", Pins("P20 P30")), + Subsignal("cke", Pins("F20 F21")), Subsignal("ba", Pins("P19 N20")), Subsignal("dm", Pins("U19 E20")), IOStandard("LVCMOS33"), diff --git a/src/soc/litex/florent/ls180pins.txt b/src/soc/litex/florent/ls180pins.txt index 650b3629..018f04e0 100644 --- a/src/soc/litex/florent/ls180pins.txt +++ b/src/soc/litex/florent/ls180pins.txt @@ -25,8 +25,8 @@ N23 | SDCARD0 data3 N24 | VDD N25 | SDRAM0 cs0_n N26 | SDRAM0 cs1_n -N27 | SDRAM0 cs2_n -N28 | SDRAM0 cs3_n +N27 | SDRAM0 cke0 +N28 | SDRAM0 cke1 N29 | VDD N30 | nc N31 | VSS @@ -55,7 +55,7 @@ E20 | VSS E21 | SDRAM0 we_n E22 | SDRAM0 ras_n E23 | SDRAM0 cas_n -E24 | SDRAM0 cke +E24 | nc E25 | VDD E26 | SDRAM0 ba0 E27 | SDRAM0 ba1 diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 61f18b8a..4ee35898 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -201,17 +201,20 @@ class GENSDRPHY(Module): pads.sel_group(pads_group) # Addresses and Commands -------------------------------------- - self.specials += [SDROutput(i=dfi.p0.address[i], o=pads.a[i]) + p0 = dfi.p0 + self.specials += [SDROutput(i=p0.address[i], o=pads.a[i]) for i in range(len(pads.a))] - self.specials += [SDROutput(i=dfi.p0.bank[i], o=pads.ba[i]) + self.specials += [SDROutput(i=p0.bank[i], o=pads.ba[i]) for i in range(len(pads.ba))] - self.specials += SDROutput(i=dfi.p0.cas_n, o=pads.cas_n) - self.specials += SDROutput(i=dfi.p0.ras_n, o=pads.ras_n) - self.specials += SDROutput(i=dfi.p0.we_n, o=pads.we_n) + self.specials += SDROutput(i=p0.cas_n, o=pads.cas_n) + self.specials += SDROutput(i=p0.ras_n, o=pads.ras_n) + self.specials += SDROutput(i=p0.we_n, o=pads.we_n) if hasattr(pads, "cke"): - self.specials += SDROutput(i=dfi.p0.cke, o=pads.cke) + for i in range(len(pads.cke)): + self.specials += SDROutput(i=p0.cke[i], o=pads.cke[i]) if hasattr(pads, "cs_n"): - self.specials += SDROutput(i=dfi.p0.cs_n, o=pads.cs_n) + for i in range(len(pads.cs_n)): + self.specials += SDROutput(i=p0.cs_n[i], o=pads.cs_n[i]) # DQ/DM Data Path ------------------------------------------------- -- 2.30.2