From 182d79eba9772e986988ae5444dcadf3f7a74ea4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 14:02:56 +0100 Subject: [PATCH] add ARM NEON as best can be done --- openpower/sv/comparison_table.mdwn | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 1881b1623..6f4e1e179 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -1,13 +1,19 @@ # ISA Comparison Table -| Name | Num of
opcodes | Scalable | Predicate
Masks | Twin
Predication | Explicit
Vector regs | 128-bit | Bigint
capability | LDST
Fault-First | Data-dependent
Fail-first | Predicate-
Result | -|------|----------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------| -| SVP64| 5 (plus prefixing) | yes | yes | yes{1} | no{2} | n/a{3} | yes{4} | yes{5} | yes{6} | yes{7} | +| Name | Num
opcodes | Scalable | Predicate
Masks | Twin
Predication | Explicit
Vector regs | 128-bit | Bigint
capability | LDST
Fault-First | Data-dependent
Fail-first | Predicate-
Result | +|------|-------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------| +| SVP64| 5{1} | yes | yes | yes{2} | no{3} | n/a{4} | yes{5} | yes{6} | yes{7} | yes{8} | +| VSX | 700+ | no | no | no | yes{9} | yes | no | no | no | no | +| NEON | ~250[10] | no | yes | no | yes | yes | no | no | no | no | -* {1}: on specific operations. -* {2}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files -* {3}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit. -* {4}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations -* {5} See [[sv/svp64/appendix]] -* {6} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] -* {7} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] +* {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]] +* {2}: on specific operations. See [[opcode_regs_deduped]] +* {3}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files +* {4}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit. +* {5}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations +* {6} See [[sv/svp64/appendix]] +* {7} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] +* {8} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] +* {9} VSX's Vector Registers are mis-named: they are PackedSIMD. +* {10} difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions). + critically depends on ARM Scalar instructions -- 2.30.2