From 1861ae9d01d8c9c6ccd84c95683c30d459510da3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 19 Sep 2015 23:21:24 +0800 Subject: [PATCH] fhdl/specials: MemoryPort.clock should always be a ClockSignal --- migen/fhdl/specials.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index e4bc6060..4137d746 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -193,10 +193,7 @@ class _MemoryPort(Special): self.re = re self.we_granularity = we_granularity self.mode = mode - if isinstance(clock_domain, str): - self.clock = ClockSignal(clock_domain) - else: - self.clock = clock_domain + self.clock = ClockSignal(clock_domain) def iter_expressions(self): for attr, target_context in [ -- 2.30.2