From 187b01df04db545587cf13116dca6e67c182e24f Mon Sep 17 00:00:00 2001
From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 4 May 2019 13:48:58 -0700
Subject: [PATCH] Move files into correct folders within ariane

---
 TLB/src/SetAssociativeCache.py          | 2 +-
 TLB/src/ariane/{ => src}/exceptcause.py | 0
 TLB/src/ariane/{ => src}/mmu.py         | 0
 TLB/src/ariane/{ => src}/plru.py        | 3 ++-
 TLB/src/ariane/{ => src}/ptw.py         | 0
 TLB/src/ariane/{ => src}/tlb.py         | 0
 TLB/src/ariane/{ => src}/tlb_content.py | 0
 TLB/src/ariane/{ => test}/test_ptw.py   | 7 ++++++-
 TLB/src/ariane/{ => test}/test_tlb.py   | 6 +++++-
 9 files changed, 14 insertions(+), 4 deletions(-)
 rename TLB/src/ariane/{ => src}/exceptcause.py (100%)
 rename TLB/src/ariane/{ => src}/mmu.py (100%)
 rename TLB/src/ariane/{ => src}/plru.py (98%)
 rename TLB/src/ariane/{ => src}/ptw.py (100%)
 rename TLB/src/ariane/{ => src}/tlb.py (100%)
 rename TLB/src/ariane/{ => src}/tlb_content.py (100%)
 rename TLB/src/ariane/{ => test}/test_ptw.py (95%)
 rename TLB/src/ariane/{ => test}/test_tlb.py (94%)

diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index 9afa1a28..0acd3488 100644
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -7,7 +7,7 @@ Python simulator of a N-way set-associative cache:
 https://github.com/vaskevich/CacheSim/blob/master/cachesim.py
 """
 import sys
-sys.path.append("../src/ariane")
+sys.path.append("ariane/src/")
 
 from nmigen import Array, Cat, Memory, Module, Signal, Mux, Elaboratable
 from nmigen.compat.genlib import fsm
diff --git a/TLB/src/ariane/exceptcause.py b/TLB/src/ariane/src/exceptcause.py
similarity index 100%
rename from TLB/src/ariane/exceptcause.py
rename to TLB/src/ariane/src/exceptcause.py
diff --git a/TLB/src/ariane/mmu.py b/TLB/src/ariane/src/mmu.py
similarity index 100%
rename from TLB/src/ariane/mmu.py
rename to TLB/src/ariane/src/mmu.py
diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/src/plru.py
similarity index 98%
rename from TLB/src/ariane/plru.py
rename to TLB/src/ariane/src/plru.py
index 7c4a4041..a98c03a6 100644
--- a/TLB/src/ariane/plru.py
+++ b/TLB/src/ariane/src/plru.py
@@ -1,4 +1,5 @@
-from nmigen import Signal, Module, Cat, Const, Elaboratable
+from nmigen import Signal, Module, Cat, Const
+from nmigen.hdl.ir import Elaboratable
 from math import log2
 
 from ptw import TLBUpdate, PTE, ASID_WIDTH
diff --git a/TLB/src/ariane/ptw.py b/TLB/src/ariane/src/ptw.py
similarity index 100%
rename from TLB/src/ariane/ptw.py
rename to TLB/src/ariane/src/ptw.py
diff --git a/TLB/src/ariane/tlb.py b/TLB/src/ariane/src/tlb.py
similarity index 100%
rename from TLB/src/ariane/tlb.py
rename to TLB/src/ariane/src/tlb.py
diff --git a/TLB/src/ariane/tlb_content.py b/TLB/src/ariane/src/tlb_content.py
similarity index 100%
rename from TLB/src/ariane/tlb_content.py
rename to TLB/src/ariane/src/tlb_content.py
diff --git a/TLB/src/ariane/test_ptw.py b/TLB/src/ariane/test/test_ptw.py
similarity index 95%
rename from TLB/src/ariane/test_ptw.py
rename to TLB/src/ariane/test/test_ptw.py
index a42a6da6..e9c5324c 100644
--- a/TLB/src/ariane/test_ptw.py
+++ b/TLB/src/ariane/test/test_ptw.py
@@ -1,3 +1,7 @@
+import sys
+sys.path.append("../src")
+sys.path.append("../../../TestUtil")
+
 from nmigen.compat.sim import run_simulation
 
 from ptw import PTW, PTE
@@ -115,8 +119,9 @@ def testbench(dut):
 
     yield
 
-    
+
 
 if __name__ == "__main__":
     dut = PTW()
     run_simulation(dut, testbench(dut), vcd_name="test_ptw.vcd")
+    print("PTW Unit Test Success")
diff --git a/TLB/src/ariane/test_tlb.py b/TLB/src/ariane/test/test_tlb.py
similarity index 94%
rename from TLB/src/ariane/test_tlb.py
rename to TLB/src/ariane/test/test_tlb.py
index bebca7f0..aab1d43c 100644
--- a/TLB/src/ariane/test_tlb.py
+++ b/TLB/src/ariane/test/test_tlb.py
@@ -1,3 +1,7 @@
+import sys
+sys.path.append("../src")
+sys.path.append("../../../TestUtil")
+
 from nmigen.compat.sim import run_simulation
 
 from tlb import TLB
@@ -58,7 +62,7 @@ def testbench(dut):
     yield
 
     yield
-    
+
 
 if __name__ == "__main__":
     dut = TLB()
-- 
2.30.2