From 187f1c999f90c3bef5b657bf386f076436149c1c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 4 Apr 2019 10:02:27 -0400 Subject: [PATCH] winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_space MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Acked-by: Nicolai Hähnle --- src/gallium/drivers/r300/r300_blit.c | 2 +- src/gallium/drivers/r300/r300_render.c | 2 +- src/gallium/drivers/r600/r600_hw_context.c | 2 +- src/gallium/drivers/r600/r600_pipe_common.c | 2 +- src/gallium/drivers/radeon/radeon_winsys.h | 6 +++++- src/gallium/drivers/radeonsi/si_dma_cs.c | 2 +- src/gallium/drivers/radeonsi/si_gfx_cs.c | 2 +- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 20 ++++++++++++------- src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 3 ++- 9 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index 01fccfbe7ed..4ac2589a9a7 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -382,7 +382,7 @@ static void r300_clear(struct pipe_context* pipe, r300_get_num_cs_end_dwords(r300); /* Reserve CS space. */ - if (!r300->rws->cs_check_space(r300->cs, dwords)) { + if (!r300->rws->cs_check_space(r300->cs, dwords, false)) { r300_flush(&r300->context, PIPE_FLUSH_ASYNC, NULL); } diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c index 211d35d0607..ed129e1a306 100644 --- a/src/gallium/drivers/r300/r300_render.c +++ b/src/gallium/drivers/r300/r300_render.c @@ -215,7 +215,7 @@ static boolean r300_reserve_cs_dwords(struct r300_context *r300, cs_dwords += r300_get_num_cs_end_dwords(r300); /* Reserve requested CS space. */ - if (!r300->rws->cs_check_space(r300->cs, cs_dwords)) { + if (!r300->rws->cs_check_space(r300->cs, cs_dwords, false)) { r300_flush(&r300->context, PIPE_FLUSH_ASYNC, NULL); flushed = TRUE; } diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index a2f5f637b20..abf5d03e4f9 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -84,7 +84,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, num_dw += 10; /* Flush if there's not enough space. */ - if (!ctx->b.ws->cs_check_space(ctx->b.gfx.cs, num_dw)) { + if (!ctx->b.ws->cs_check_space(ctx->b.gfx.cs, num_dw, false)) { ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL); } } diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index 664ca268b37..a90166148a1 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -286,7 +286,7 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, * engine busy while uploads are being submitted. */ num_dw++; /* for emit_wait_idle below */ - if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) || + if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw, false) || ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 || !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) { ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL); diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 770db2857d5..5576a64f29b 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -572,8 +572,12 @@ struct radeon_winsys { * * \param cs A command stream. * \param dw Number of CS dwords requested by the caller. + * \param force_chaining Chain the IB into a new buffer now to discard + * the CP prefetch cache (to emulate PKT3_REWIND) + * \return true if there is enough space */ - bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw); + bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw, + bool force_chaining); /** * Return the buffer list. diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c index 8f2e15833b6..8bc5d0ed209 100644 --- a/src/gallium/drivers/radeonsi/si_dma_cs.c +++ b/src/gallium/drivers/radeonsi/si_dma_cs.c @@ -164,7 +164,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, */ num_dw++; /* for emit_wait_idle below */ if (!ctx->sdma_uploads_in_progress && - (!ws->cs_check_space(ctx->dma_cs, num_dw) || + (!ws->cs_check_space(ctx->dma_cs, num_dw, false) || ctx->dma_cs->used_vram + ctx->dma_cs->used_gart > 64 * 1024 * 1024 || !radeon_cs_memory_below_limit(ctx->screen, ctx->dma_cs, vram, gtt))) { si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL); diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index c81718950a4..121ab75c08b 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -55,7 +55,7 @@ void si_need_gfx_cs_space(struct si_context *ctx) ctx->vram = 0; unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx); - if (!ctx->ws->cs_check_space(cs, need_dwords)) + if (!ctx->ws->cs_check_space(cs, need_dwords, false)) si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index eb973bf8102..555150a7018 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -1031,7 +1031,8 @@ static bool amdgpu_cs_validate(struct radeon_cmdbuf *rcs) return true; } -static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) +static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, + bool force_chaining) { struct amdgpu_ib *ib = amdgpu_ib(rcs); struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib); @@ -1048,16 +1049,21 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) ib->max_check_space_size = MAX2(ib->max_check_space_size, safe_byte_size); - if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type)) - return false; + /* If force_chaining is true, we can't return. We have to chain. */ + if (!force_chaining) { + if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type)) + return false; - ib->max_ib_size = MAX2(ib->max_ib_size, requested_size); + ib->max_ib_size = MAX2(ib->max_ib_size, requested_size); - if (rcs->current.max_dw - rcs->current.cdw >= dw) - return true; + if (rcs->current.max_dw - rcs->current.cdw >= dw) + return true; + } - if (!amdgpu_cs_has_chaining(cs)) + if (!amdgpu_cs_has_chaining(cs)) { + assert(!force_chaining); return false; + } /* Allocate a new chunk */ if (rcs->num_prev >= rcs->max_prev) { diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index 670d2f57de6..7de748a4aff 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -424,7 +424,8 @@ static bool radeon_drm_cs_validate(struct radeon_cmdbuf *rcs) return status; } -static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) +static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, + bool force_chaining) { assert(rcs->current.cdw <= rcs->current.max_dw); return rcs->current.max_dw - rcs->current.cdw >= dw; -- 2.30.2