From 18ad0d69caf7357c80af3d190f0f64f8db08916e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 31 Aug 2021 21:20:02 +0100 Subject: [PATCH] update ready/valid in shift_rot test_pipe_caller --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index ac7a4092..ea1aba38 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -106,18 +106,18 @@ class TestRunner(unittest.TestCase): yield from set_alu_inputs(alu, pdecode2, simulator) # set valid for one cycle, propagate through pipeline... - yield alu.p.valid_i.eq(1) + yield alu.p.i_valid.eq(1) yield - yield alu.p.valid_i.eq(0) + yield alu.p.i_valid.eq(0) opname = code.split(' ')[0] yield from simulator.call(opname) index = simulator.pc.CIA.value//4 - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid while not vld: yield - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid yield alu_out = yield alu.n.o_data.o.data @@ -140,7 +140,7 @@ class TestRunner(unittest.TestCase): m.submodules.alu = alu = ShiftRotBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) - comb += alu.n.ready_i.eq(1) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) -- 2.30.2