From 18b19d17be83b2c6d74f28bd6bd8e127b129dcaa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Jun 2020 18:28:36 +0100 Subject: [PATCH] allow Mem initialisation in ISACaller --- src/soc/decoder/pseudo/pywriter.py | 4 ++-- src/soc/experiment/compalu_multi.py | 1 - src/soc/fu/compunits/test/test_compunit.py | 3 ++- src/soc/fu/ldst/test/test_pipe_caller.py | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py index 1fa845d3..02ccce7f 100644 --- a/src/soc/decoder/pseudo/pywriter.py +++ b/src/soc/decoder/pseudo/pywriter.py @@ -116,8 +116,8 @@ class PyISAWriter(ISA): classes = ', '.join(['ISACaller'] + self.pages_written) f.write('class ISA(%s):\n' % classes) - f.write(' def __init__(self, dec, regs, sprs, cr):\n') - f.write(' super().__init__(dec, regs, sprs, cr)\n') + f.write(' def __init__(self, dec, regs, sprs, cr, mem):\n') + f.write(' super().__init__(dec, regs, sprs, cr, mem)\n') f.write(' self.instrs = {\n') for page in self.pages_written: f.write(' **self.%s_instrs,\n' % page) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 090c22d4..63a6d684 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -150,7 +150,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): self.data_o = self.dest[0] # Dest out self.done_o = cu.done_o - def _mux_op(self, m, sl, op_is_imm, imm, i): # select imm if opcode says so. however also change the latch # to trigger *from* the opcode latch instead. diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 69c9d0fc..d35ad27d 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -131,7 +131,8 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - sim = ISA(pdecode2, test.regs, test.sprs, 0) + print ("test", test.name, test.mem) + sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py index adceb4cf..8716f4cd 100644 --- a/src/soc/fu/ldst/test/test_pipe_caller.py +++ b/src/soc/fu/ldst/test/test_pipe_caller.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs +from soc.decoder.isa.caller import special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) -- 2.30.2