From 18bf6f848b020810b66f5da90cdcaf5789f9aebe Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 3 Oct 2022 12:06:56 +0100 Subject: [PATCH] --- openpower/sv/svp64/discussion.mdwn | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn index d438df693..a57331cb4 100644 --- a/openpower/sv/svp64/discussion.mdwn +++ b/openpower/sv/svp64/discussion.mdwn @@ -222,7 +222,7 @@ four aspects: ## answers to 2, RM Modes -Normal Mode: +**Normal Mode:** * simple mode is straight vectorisation. * reduce mode @@ -232,9 +232,15 @@ Normal Mode: simple mode is fine including on predication but has a CHANGE OF BEHAVIOUR. first bit of src/dest is used when zeroing is on, but first ENABLED bit of predicate is used when VL>1. -reduce mode is unaffected (meaningless) +reduce mode is unaffected (meaningless) on a scalar operation -## answers to 4, loops +fail-first with or without VLI, should be unaffected, but what should VL be truncated to? the override VL=1? (or VL=0 when VLI is set?) + +saturation mode is fine + +predicate-result should be fine as well. + +## answers to 4, loops/uses **REMAP** -- 2.30.2