From 18c2dc9b791eb04d9205d5fc98f1eb909c469e69 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 31 Mar 2020 20:23:14 -0700 Subject: [PATCH] add test case for https://github.com/nmigen/nmigen/issues/344 --- src/test_run_simulation_bug.py | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 src/test_run_simulation_bug.py diff --git a/src/test_run_simulation_bug.py b/src/test_run_simulation_bug.py new file mode 100644 index 0000000..df4bb89 --- /dev/null +++ b/src/test_run_simulation_bug.py @@ -0,0 +1,30 @@ +from nmigen import Signal, Module, Elaboratable +from nmigen.compat.sim import run_simulation + +# test for https://github.com/nmigen/nmigen/issues/344 + + +class MyModule(Elaboratable): + def __init__(self): + self.a = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.a.eq(~self.a) + return m + + +def test1(): + dut = MyModule() + + def generator(): + for _i in range(10): + print((yield dut.a)) + yield + + run_simulation(dut, generator(), + vcd_name="test_run_simulation_bug.vcd") + + +if __name__ == '__main__': + test1() -- 2.30.2