From 18ebb86edbade4a94833dead59d69fddd980f5bd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 29 Sep 2019 11:25:34 -0700 Subject: [PATCH] FDCE_1 does not have IS_CLR_INVERTED --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ee9d48684..cf39bd45b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -408,7 +408,7 @@ module FDCE_1 ( always @* Q = \$nextQ ; `else assign \$currQ = Q; - always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; `endif endmodule -- 2.30.2