From 18eebfeb76a9df381e10ea16fb3bf78576fe62bd Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Mon, 10 Aug 2020 09:05:53 -0700 Subject: [PATCH] mmu.py add line I forgot to translate from mmu.vhdl --- src/soc/experiment/mmu.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 8775652b..d5cba5a2 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -566,6 +566,7 @@ class AddrShifter(Elaboratable): # pt_valid := r.pt3_valid; with m.Else(): comb += pgtbl.eq(r.pt3_valid) + comb += pt_valid.eq(r.pt3_valid) # end if; # -- rts == radix tree size, # address bits being translated -- 2.30.2