From 18fdfbdc32f204d6728c1ad57a693b1a6ad0aec9 Mon Sep 17 00:00:00 2001
From: Christoph Bumiller <e0425955@student.tuwien.ac.at>
Date: Mon, 11 Mar 2013 17:34:05 +0100
Subject: [PATCH] nv50/ir: add CCTL (cache control) op

---
 src/gallium/drivers/nv50/codegen/nv50_ir.h    |  3 +++
 .../drivers/nv50/codegen/nv50_ir_peephole.cpp |  2 +-
 .../drivers/nv50/codegen/nv50_ir_print.cpp    |  1 +
 .../drivers/nv50/codegen/nv50_ir_target.cpp   |  6 ++---
 .../nvc0/codegen/nv50_ir_emit_nvc0.cpp        | 25 +++++++++++++++++++
 5 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir.h b/src/gallium/drivers/nv50/codegen/nv50_ir.h
index 7862724411e..236673c2489 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir.h
@@ -153,6 +153,7 @@ enum operation
    OP_VSHR,
    OP_VSHL,
    OP_VSEL,
+   OP_CCTL, // cache control
    OP_LAST
 };
 
@@ -199,6 +200,8 @@ enum operation
 #define NV50_IR_SUBOP_ATOM_XOR      7
 #define NV50_IR_SUBOP_ATOM_CAS      8
 #define NV50_IR_SUBOP_ATOM_EXCH     9
+#define NV50_IR_SUBOP_CCTL_IV      5
+#define NV50_IR_SUBOP_CCTL_IVALL   6
 #define NV50_IR_SUBOP_SUST_IGN     0
 #define NV50_IR_SUBOP_SUST_TRAP    1
 #define NV50_IR_SUBOP_SUST_SDCL    3
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
index 2926907cdf1..aee3d55c22a 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
@@ -1791,7 +1791,7 @@ MemoryOpt::runOpt(BasicBlock *bb)
             purgeRecords(NULL, FILE_MEMORY_SHARED);
             purgeRecords(NULL, FILE_SHADER_OUTPUT);
          } else
-         if (ldst->op == OP_ATOM) {
+         if (ldst->op == OP_ATOM || ldst->op == OP_CCTL) {
             if (ldst->src(0).getFile() == FILE_MEMORY_GLOBAL) {
                purgeRecords(NULL, FILE_MEMORY_LOCAL);
                purgeRecords(NULL, FILE_MEMORY_GLOBAL);
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_print.cpp
index 1c3b768259a..c7121bf1340 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_print.cpp
@@ -183,6 +183,7 @@ const char *operationStr[OP_LAST + 1] =
    "vshr",
    "vshl",
    "vsel",
+   "cctl",
    "(invalid)"
 };
 
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
index 1b6d1830ee5..63da152d164 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
@@ -53,7 +53,7 @@ const uint8_t Target::operationSrcNr[OP_LAST + 1] =
    2, 3, 2, 3,             // POPCNT, INSBF, EXTBF, PERMT
    2, 2,                   // ATOM, BAR
    2, 2, 2, 2, 3, 2,       // VADD, VAVG, VMIN, VMAX, VSAD, VSET,
-   2, 2, 2,                // VSHR, VSHL, VSEL
+   2, 2, 2, 1,             // VSHR, VSHL, VSEL, CCTL
    0
 };
 
@@ -123,8 +123,8 @@ const OpClass Target::operationClass[OP_LAST + 1] =
    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
    // VSAD, VSET, VSHR, VSHL
    OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR, OPCLASS_VECTOR,
-   // VSEL
-   OPCLASS_VECTOR,
+   // VSEL, CCTL
+   OPCLASS_VECTOR, OPCLASS_CONTROL,
    OPCLASS_PSEUDO // LAST
 };
 
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
index 64207d71aac..ba2f73be9c2 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
@@ -82,6 +82,7 @@ private:
    void emitMOV(const Instruction *);
    void emitATOM(const Instruction *);
    void emitMEMBAR(const Instruction *);
+   void emitCCTL(const Instruction *);
 
    void emitINTERP(const Instruction *);
    void emitPFETCH(const Instruction *);
@@ -1885,6 +1886,27 @@ CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
    emitPredicate(i);
 }
 
+void
+CodeEmitterNVC0::emitCCTL(const Instruction *i)
+{
+   code[0] = 0x00000005 | (i->subOp << 5);
+
+   if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
+      code[1] = 0x98000000;
+      srcAddr32(i->src(0), 28, 2);
+   } else {
+      code[1] = 0xd0000000;
+      setAddress24(i->src(0));
+   }
+   if (uses64bitAddress(i))
+      code[1] |= 1 << 26;
+   srcId(i->src(0).getIndirect(0), 20);
+
+   emitPredicate(i);
+
+   defId(i, 0, 14);
+}
+
 void
 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
 {
@@ -2348,6 +2370,9 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
    case OP_MEMBAR:
       emitMEMBAR(insn);
       break;
+   case OP_CCTL:
+      emitCCTL(insn);
+      break;
    case OP_VSHL:
       emitVSHL(insn);
       break;
-- 
2.30.2