From 1902732ee68b610fba2f286b074ac29ce95e3803 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 15 Oct 2020 15:53:00 +0100 Subject: [PATCH] disable gpio in litex core --- src/soc/litex/florent/libresoc/core.py | 4 ++-- src/soc/litex/florent/versa_ecp5.py | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 3bc76798..9703cbfe 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -166,7 +166,7 @@ class LibreSoC(CPU): jtag_en = ('jtag' in variant) or variant == 'ls180' - if variant != "ls180": + if "gpiotest" in variant: self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30) if jtag_en: self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29) @@ -240,7 +240,7 @@ class LibreSoC(CPU): self.cpu_params.update(make_wb_bus("dbus", dbus)) self.cpu_params.update(make_wb_slave("ics_wb", ics)) self.cpu_params.update(make_wb_slave("icp_wb", icp)) - if variant != "ls180": + if "gpiotest" in variant: self.cpu_params.update(make_wb_slave("gpio_wb", gpio)) if jtag_en: self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True)) diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py index e2e31d14..c9938fea 100755 --- a/src/soc/litex/florent/versa_ecp5.py +++ b/src/soc/litex/florent/versa_ecp5.py @@ -30,6 +30,7 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC): cpu_type = "external", cpu_cls = LibreSoC, cpu_variant = "standardjtag", + cpu_variant = "standardjtagnoirq", #cpu_cls = Microwatt, device = "LFE5UM", **kwargs) -- 2.30.2