From 1909a1a914ebed46d02426c1502af3277e6f1362 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 23:22:37 +0100 Subject: [PATCH] oops forgot to initialise base class of TestMemLoadStoreUnit --- src/soc/experiment/lsmem.py | 7 +------ src/soc/experiment/pi2ls.py | 1 + 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py index d8292920..da9c73ac 100644 --- a/src/soc/experiment/lsmem.py +++ b/src/soc/experiment/lsmem.py @@ -6,15 +6,10 @@ from nmigen.cli import rtlil class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): - def __init__(self, addr_wid=32, mask_wid=4, data_wid=32): - super().__init__() - self.regwid = data_wid - self.addrwid = addr_wid - self.mask_wid = mask_wid def elaborate(self, platform): m = Module() - regwid, addrwid, mask_wid = self.regwid, self.addrwid, self.mask_wid + regwid, addrwid, mask_wid = self.data_wid, self.addr_wid, self.mask_wid adr_lsb = self.adr_lsbs # limit TestMemory to 2^6 entries of regwid size diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 8e6b2ccc..32ed0a8a 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -34,6 +34,7 @@ class Pi2LSUI(Elaboratable): def __init__(self, name, pi=None, lsui=None, regwid=64, mask_wid=8, addrwid=48): + print ("pi2lsui reg mask addr", regwid, mask_wid, addrwid) self.addrbits = mask_wid if pi is None: pi = PortInterface(name="%s_pi", regwid=regwid, addrwid=addrwid) -- 2.30.2