From 191233d941a11761753ceaf13d2bfb11a5201ef7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 12:15:29 +0100 Subject: [PATCH] add checks for RVC registers to sv template --- riscv/insn_template_sv.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 3ff09e8..83c9b44 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -35,6 +35,18 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) #endif #ifdef USING_REG_RS2 insn.sv_check_reg(true, s_insn.rs3()) | +#endif +#ifdef USING_REG_RVC_RS1 + insn.sv_check_reg(true, s_insn.rvc_rs1()) | +#endif +#ifdef USING_REG_RVC_RS1S + insn.sv_check_reg(true, s_insn.rvc_rs1s()) | +#endif +#ifdef USING_REG_RVC_RS2 + insn.sv_check_reg(true, s_insn.rvc_rs2()) | +#endif +#ifdef USING_REG_RVC_RS2S + insn.sv_check_reg(true, s_insn.rvc_rs2s()) | #endif // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb) #ifdef USING_REG_FRD @@ -48,6 +60,12 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) #endif #ifdef USING_REG_FRS2 insn.sv_check_reg(false, s_insn.rs3()) | +#endif +#ifdef USING_REG_RVC_FRS2 + insn.sv_check_reg(false, s_insn.rvc_rs2()) | +#endif +#ifdef USING_REG_RVC_FRS2S + insn.sv_check_reg(false, s_insn.rvc_rs2s()) | #endif false; // save a few cycles by |ing the checks together. -- 2.30.2