From 19134154fec7e4fb7c7e67c8bf4e4660f6820c12 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Aug 2020 14:00:00 +0100
Subject: [PATCH] add quick test of litex bios IMM64 macro

---
 src/soc/decoder/isa/caller.py |  3 ++-
 src/soc/simulator/test_sim.py | 44 ++++++++++++++++++++++-------------
 2 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 9053d268..7a25bf0b 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -532,8 +532,9 @@ class ISACaller:
     def get_assembly_name(self):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+        dec_insn = yield self.dec2.e.do.insn
         asmcode = yield self.dec2.dec.op.asmcode
-        print("get assembly name asmcode", asmcode)
+        print("get assembly name asmcode", asmcode, hex(dec_insn))
         asmop = insns.get(asmcode, None)
         int_op = yield self.dec2.dec.op.internal_op
 
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 16a3237e..f2477a1f 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -49,6 +49,33 @@ class GeneralTestCases(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
+    def test_0_litex_bios_r1(self):
+        """litex bios IMM64 macro test
+        """
+        lst = [ "addis     1,0,0",
+                 "ori     1,1,0",
+                 "rldicr  1,1,32,31",
+                 "oris    1,1,256",
+                 "ori     1,1,3832",
+               ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [1], initial_mem={})
+
+    @unittest.skip("disable")
+    def test_0_litex_trampoline(self):
+        lst = ["tdi   0,0,0x48",
+               "b     0x28",
+               "mfmsr r11",
+               "bcl 20,31,4",
+               "mflr r10",
+               "addi r10,r10,20",
+               "mthsrr0 r10",
+               "mthsrr1 r11",
+               "hrfid",
+               ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [], initial_mem={})
+
     @unittest.skip("disable")
     def test_0_cmp(self):
         lst = ["addi 6, 0, 0x10",
@@ -243,20 +270,6 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
-    def test_litex_trampoline(self):
-        lst = ["tdi   0,0,0x48",
-               "b     0x28",
-               "mfmsr r11",
-               "bcl 20,31,4",
-               "mflr r10",
-               "addi r10,r10,20",
-               "mthsrr0 r10",
-               "mthsrr1 r11",
-               "hrfid",
-               ]
-        with Program(lst, bigendian) as program:
-            self.run_tst_program(program, [], initial_mem={})
-
     def test_30_addis(self):
         lst = [  # "addi 0, 0, 5",
             "addis 12, 0, 0",
@@ -310,8 +323,7 @@ class DecoderBase:
                 yield Settle()
 
         sim.add_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                           traces=[]):
+        with sim.write_vcd("pdecode_simulator.vcd"):
             sim.run()
 
         return simulator
-- 
2.30.2