From 19643ab8d9270de7440a2519104f70c3f3af80bc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 7 Dec 2021 12:11:38 +0000 Subject: [PATCH] add discussion links and bugreport --- src/soc/experiment/dcache.py | 2 ++ src/soc/experiment/icache.py | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 872ed5bb..abef5d6d 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -13,6 +13,8 @@ Links: * https://libre-soc.org/3d_gpu/architecture/set_associative_cache.jpg * https://bugs.libre-soc.org/show_bug.cgi?id=469 +* https://libre-soc.org/irclog-microwatt/%23microwatt.2021-12-07.log.html + (discussion about brams for ECP5) """ diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 845ed5ec..470f5718 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -17,6 +17,13 @@ TODO (in no specific order): write TAG_BITS width which may not match full ram blocks and might cause muxes to be inferred for "partial writes". * Check if making the read size of PLRU a ROM helps utilization + +Links: + +* https://bugs.libre-soc.org/show_bug.cgi?id=485 +* https://libre-soc.org/irclog-microwatt/%23microwatt.2021-12-07.log.html + (discussion about brams for ECP5) + """ from enum import (Enum, unique) -- 2.30.2