From 19729d85680d66604bd58ecc49007f6983855729 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 16 Dec 2021 14:37:06 +0000 Subject: [PATCH] set_mmu_spr was using the slow-SPR index for the regfile not the actual 10-bit SPR number. hence trying to set PRTBL fails --- src/soc/experiment/mmu.py | 5 +++++ src/soc/simple/test/test_core.py | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 83574929..e7010584 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -372,6 +372,11 @@ class MMU(Elaboratable): self.rin = rin = RegStage("r_in") r = RegStage("r") + # get access to prtbl and pid for debug / testing purposes ONLY + # (actually, not needed, because setup_regs() triggers mmu direct) + # self._prtbl = r.prtbl + # self._pid = r.pid + l_in = self.l_in l_out = self.l_out d_out = self.d_out diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index cbb093d2..0c3ad1e2 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -60,7 +60,7 @@ def set_mmu_spr(name, i, val, core): # important keep pep8 formatting yield fsm.mmu.l_in.rs.eq(val) yield yield fsm.mmu.l_in.mtspr.eq(0) - print("mmu_spr was updated") + print("mmu_spr %s %d was updated %x" % (name, i, val)) def setup_regs(pdecode2, core, test): @@ -128,7 +128,10 @@ def setup_regs(pdecode2, core, test): sprname = spr_dict[sprname].SPR if sprname == 'XER': continue + print ('set spr %s val %x' % (sprname, val)) + fast = spr_to_fast_reg(sprname) + if fast is None: # match behaviour of SPRMap in power_decoder2.py for i, x in enumerate(SPR): @@ -138,7 +141,7 @@ def setup_regs(pdecode2, core, test): if sprname not in mmu_sprs: yield sregs.memory._array[i].eq(val) else: - yield from set_mmu_spr(sprname, i, val, core) + yield from set_mmu_spr(sprname, x.value, val, core) else: print("setting fast reg %d (%s) to %x" % (fast, sprname, val)) -- 2.30.2