From 19973c2bb3a343e70c4699f2388251afd36fd542 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 30 May 2023 00:51:07 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index eca3eeaca..3c94ca182 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -52,7 +52,7 @@ actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable Vector instructions on the SFFS Subset and closer to 10 million 64-bit True-Scalable Vector instructions if introduced on VSX. SVP64, the instruction format used by Simple-V, is therefore best viewed as an -orthogonal RISC-paradigm "Prefixing" subsystem instead. +orthogonal RISC-paradigm "Loop Prefixing" subsystem instead. [^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir) [^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir) -- 2.30.2