From 19a6157478f6bb863f48b700d062a641001757bb Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 30 Mar 2015 00:44:56 +0800 Subject: [PATCH] platforms/lx9_microboard,usrp_b100: fix bitgen opts --- mibuild/platforms/lx9_microboard.py | 4 ++-- mibuild/platforms/usrp_b100.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index cbf03b3b..077d0a0b 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -110,8 +110,8 @@ class Platform(XilinxPlatform): self.add_platform_command(""" CONFIG VCCAUX = "3.3"; """) - self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" - self.ise_commands = """ + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" + self.toolchain.ise_commands = """ promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit """ diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py index ac2edb49..ff6413e0 100644 --- a/mibuild/platforms/usrp_b100.py +++ b/mibuild/platforms/usrp_b100.py @@ -118,7 +118,7 @@ class Platform(XilinxPlatform): def __init__(self): XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io) - self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) -- 2.30.2