From 19b55b3533295a48c731765fa4813395f3bc9570 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 22:50:57 +0100
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index bcada5b52..eab4c99ba 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -223,7 +223,7 @@ than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
 **RC1** as if Rc=1, stores CRs *but not the result*
 
-For LD/ST Modes, see and [[sv/ldst]].  Immediate and Indexed LD/ST
+For LD/ST Modes, see [[sv/ldst]].  For Branch modes, see [[sv/branch]] Immediate and Indexed LD/ST
 are both different, in order to support a large range of features
 normally found in Vector ISAs.
 
-- 
2.30.2